Crate riscv 

Shared support for RISC-V architectures.

Modules

csr

Tock Register interface for using CSR registers.

dma_fence

pmp

pseudo_instructions

Define missing RISC-V pseudo instructions using assembly macros.

support

Core low-level operations.

syscall

Kernel-userland system call interface for RISC-V architecture.

thread_id

RISC-V support for getting the running thread ID.

Macros

xlen_macros

Enums

PermissionMode

The various privilege levels in RISC-V.

Constants

XLEN

XLEN is the width of an integer register in bits (either 32 or 64).

XLEN_LOG2

Functions

_start_trap

This is the trap handler function. This code is called on all traps, including interrupts, exceptions, and system calls from applications.

configure_trap_handler^⚠

Tell the MCU what address the trap handler is located at, and initialize mscratch to zero, indicating kernel execution.

initialize_ram_jump_to_main^⚠

Entry point of all programs

print_mcause^⚠

Print a readable string for an mcause reason.

print_riscv_state^⚠

Prints out RISCV machine state, including basic system registers (mcause, mstatus, mtvec, mepc, mtval, interrupt status).

semihost_command^⚠

RISC-V semihosting needs three exact instructions in uncompressed form.