Struct RiscvCoherentDmaFence 

pub struct RiscvCoherentDmaFence { /* private fields */ }

An implementation of [DmaFence] for RISC-V systems with cache-coherent DMA memory accesses.

The provided release and acquire methods use opaque assembly blocks and RISC-V FENCE instructions to make prior writes to DMA buffers visible to DMA devices, and DMA writes visible to prior memory reads, respectively.

These primitives are sufficient to implement the release / acquire semantics of [DmaFence] for cache-coherent platforms where all memory writes written back are immediately visible to DMA devices, and all DMA writes are immediately visible to CPU fetches.

For platforms where explicit cache-flush instructions are required, this implementation alone is insufficient and must be extended with the necessary platform-specific instructions.

Implementations

impl RiscvCoherentDmaFence

pub unsafe fn new() -> RiscvCoherentDmaFence

Construct a new RiscvCoherentDmaFence.

Refer to the type-level documentation and the documentation of the DmaFence trait and its implementation for RiscvCoherentDmaFence for more details.

Safety

This RiscvCoherentDmaFence implementation is insufficient for platforms with non-coherent DMA, where explicit cache-flush instructions are required. By using unsafe, callers of this function promise that the resulting instance is not used for non-coherent DMA mappings.

Trait Implementations

impl Clone for RiscvCoherentDmaFence

fn clone(&self) -> RiscvCoherentDmaFence

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for RiscvCoherentDmaFence

impl Debug for RiscvCoherentDmaFence

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl DmaFence for RiscvCoherentDmaFence

Available on non-riscv_bare_metal only.

fn release<T>(self, _slice_ptr: *mut [T])

Expose prior writes to in-memory buffers to subsequent DMA operations.

fn acquire<T>(self, _slice_ptr: *mut [T])

Expose prior writes by DMA peripherals to subsequent memory reads.