pub trait LiteXSoCRegisterConfiguration {
type ReadOnly8: BaseReadableRegister<u8, Reg = ()>;
type WriteOnly8: BaseWriteableRegister<u8, Reg = ()>;
type ReadWrite8: BaseReadableRegister<u8, Reg = ()> + BaseWriteableRegister<u8, Reg = ()>;
type ReadOnly16: BaseReadableRegister<u16, Reg = ()>;
type WriteOnly16: BaseWriteableRegister<u16, Reg = ()>;
type ReadWrite16: BaseReadableRegister<u16, Reg = ()> + BaseWriteableRegister<u16, Reg = ()>;
type ReadOnly32: BaseReadableRegister<u32, Reg = ()>;
type WriteOnly32: BaseWriteableRegister<u32, Reg = ()>;
type ReadWrite32: BaseReadableRegister<u32, Reg = ()> + BaseWriteableRegister<u32, Reg = ()>;
type ReadOnly64: BaseReadableRegister<u64, Reg = ()>;
type WriteOnly64: BaseWriteableRegister<u64, Reg = ()>;
type ReadWrite64: BaseReadableRegister<u64, Reg = ()> + BaseWriteableRegister<u64, Reg = ()>;
}
Expand description
Register abstraction types collection
This trait defines a collection of types for a certain set of
LiteX configuration options. It provides types with all
accessibility constraints (Read
, Write
, ReadWrite
) for
every defined register width.
All types must be over a common register layout configuration, having identical
- base integer width
- CSR data width
- endianness
§Generic Register Type Arguments
Usually registers are generic over a RegisterLongName
type
arguments, such that the Field
and FieldValue
arguments of
the various methods make sense.
Unfortunately, those generic type arguments cannot be passed through associated types in traits until generic associated types stabilize.
In the meantime, the types ReadRegWrapper
, WriteRegWrapper
and ReadWriteRegWrapper
can be used to access fields in a
register as commonly done in tock-registers:
pub struct LiteXUartRegisters<R: LiteXSoCRegisterConfiguration> {
txfull: R::ReadOnly8,
}
register_bitfields![u8,
txfull [
full OFFSET(0) NUMBITS(1) []
],
];
ReadRegWrapper::wrap(®s.txfull).is_set(txfull::full)