Struct MpuRegisters 

#[repr(C)]
pub struct MpuRegisters {
    pub mpu_type: ReadOnly<u32, Register>,
    pub ctrl: ReadWrite<u32, Register>,
    pub rnr: ReadWrite<u32, Register>,
    pub rbar: ReadWrite<u32, Register>,
    pub rasr: ReadWrite<u32, Register>,
}

MPU Registers for the Cortex-M3, Cortex-M4 and Cortex-M7 families Described in section 4.5 of http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf

Fields

mpu_type: ReadOnly<u32, Register>

Indicates whether the MPU is present and, if so, how many regions it supports.

ctrl: ReadWrite<u32, Register>

The control register:

• Enables the MPU (bit 0).
• Enables MPU in hard-fault, non-maskable interrupt (NMI).
• Enables the default memory map background region in privileged mode.

rnr: ReadWrite<u32, Register>

Selects the region number (zero-indexed) referenced by the region base address and region attribute and size registers.

rbar: ReadWrite<u32, Register>

Defines the base address of the currently selected MPU region.

rasr: ReadWrite<u32, Register>

Defines the region size and memory attributes of the selected MPU region. The bits are defined as in 4.5.5 of the Cortex-M4 user guide.