riscv/
pseudo_instructions.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2026.
4
5//! Define missing RISC-V pseudo instructions using assembly macros.
6//!
7//! The RISC-V spec includes numerous pseudo instructions to help with writing
8//! RISC-V assembly. However, somewhat bafflingly, there are no pseudo
9//! instructions for making operations XLEN bits long. This makes it difficult
10//! to write general assembly code that works on both RV32 and RV64 systems,
11//! where the assembly only needs to operate on different XLENs.
12//!
13//! `xlen_macros!` defines macros `lx` and `sx`, which function as
14//! pseudoinstructions for loading and storing XLEN-sized values.
15
16#[cfg(any(doc, target_arch = "riscv32"))]
17#[macro_export]
18macro_rules! xlen_macros[() => [r"
19    .macro sx src, dest
20        sw \src, \dest
21    .endm
22    .macro lx dest, src
23        lw \dest, \src
24    .endm
25"]];
26
27#[cfg(target_arch = "riscv64")]
28#[macro_export]
29macro_rules! xlen_macros[() => [r"
30    .macro sx src, dest
31        sd \src, \dest
32    .endm
33    .macro lx dest, src
34        ld \dest, \src
35    .endm
36"]];
riscv/pseudo_instructions.rs

riscv/
pseudo_instructions.rs
