riscv/csr/
mod.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Tock Register interface for using CSR registers.
6
7use riscv_csr::csr::{
8    ReadWriteRiscvCsr, MCAUSE, MCYCLE, MCYCLEH, MEPC, MIE, MINSTRET, MINSTRETH, MIP, MSCRATCH,
9    MSECCFG, MSECCFGH, MSTATUS, MTVAL, MTVEC, PMPADDR0, PMPADDR1, PMPADDR10, PMPADDR11, PMPADDR12,
10    PMPADDR13, PMPADDR14, PMPADDR15, PMPADDR16, PMPADDR17, PMPADDR18, PMPADDR19, PMPADDR2,
11    PMPADDR20, PMPADDR21, PMPADDR22, PMPADDR23, PMPADDR24, PMPADDR25, PMPADDR26, PMPADDR27,
12    PMPADDR28, PMPADDR29, PMPADDR3, PMPADDR30, PMPADDR31, PMPADDR32, PMPADDR33, PMPADDR34,
13    PMPADDR35, PMPADDR36, PMPADDR37, PMPADDR38, PMPADDR39, PMPADDR4, PMPADDR40, PMPADDR41,
14    PMPADDR42, PMPADDR43, PMPADDR44, PMPADDR45, PMPADDR46, PMPADDR47, PMPADDR48, PMPADDR49,
15    PMPADDR5, PMPADDR50, PMPADDR51, PMPADDR52, PMPADDR53, PMPADDR54, PMPADDR55, PMPADDR56,
16    PMPADDR57, PMPADDR58, PMPADDR59, PMPADDR6, PMPADDR60, PMPADDR61, PMPADDR62, PMPADDR63,
17    PMPADDR7, PMPADDR8, PMPADDR9, PMPCFG0, PMPCFG1, PMPCFG10, PMPCFG11, PMPCFG12, PMPCFG13,
18    PMPCFG14, PMPCFG15, PMPCFG2, PMPCFG3, PMPCFG4, PMPCFG5, PMPCFG6, PMPCFG7, PMPCFG8, PMPCFG9,
19    STVEC, UTVEC,
20};
21use tock_registers::fields::FieldValue;
22use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
23
24pub mod mcause;
25pub mod mcycle;
26pub mod mepc;
27pub mod mie;
28pub mod minstret;
29pub mod mip;
30pub mod mscratch;
31pub mod mseccfg;
32pub mod mstatus;
33pub mod mtval;
34pub mod mtvec;
35pub mod pmpaddr;
36pub mod pmpconfig;
37pub mod stvec;
38pub mod utvec;
39
40// NOTE! We default to 32 bit if this is being compiled for debug/testing. We do
41// this by using `cfg` that check for either the architecture is `riscv32` (true
42// if we are compiling for a rv32i target), OR if the target OS is set to
43// something (as it would be if compiled for a host OS).
44
45pub struct CSR {
46    #[cfg(not(target_arch = "riscv64"))]
47    pub minstreth: ReadWriteRiscvCsr<usize, minstret::minstreth::Register, MINSTRETH>,
48    pub minstret: ReadWriteRiscvCsr<usize, minstret::minstret::Register, MINSTRET>,
49
50    #[cfg(not(target_arch = "riscv64"))]
51    pub mcycleh: ReadWriteRiscvCsr<usize, mcycle::mcycleh::Register, MCYCLEH>,
52    pub mcycle: ReadWriteRiscvCsr<usize, mcycle::mcycle::Register, MCYCLE>,
53
54    #[cfg(not(target_arch = "riscv64"))]
55    pub pmpcfg0: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG0>,
56    #[cfg(not(target_arch = "riscv64"))]
57    pub pmpcfg1: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG1>,
58    pub pmpcfg2: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG2>,
59    #[cfg(not(target_arch = "riscv64"))]
60    pub pmpcfg3: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG3>,
61    pub pmpcfg4: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG4>,
62    #[cfg(not(target_arch = "riscv64"))]
63    pub pmpcfg5: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG5>,
64    pub pmpcfg6: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG6>,
65    #[cfg(not(target_arch = "riscv64"))]
66    pub pmpcfg7: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG7>,
67    pub pmpcfg8: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG8>,
68    #[cfg(not(target_arch = "riscv64"))]
69    pub pmpcfg9: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG9>,
70    pub pmpcfg10: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG10>,
71    #[cfg(not(target_arch = "riscv64"))]
72    pub pmpcfg11: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG11>,
73    pub pmpcfg12: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG12>,
74    #[cfg(not(target_arch = "riscv64"))]
75    pub pmpcfg13: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG13>,
76    pub pmpcfg14: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG14>,
77    #[cfg(not(target_arch = "riscv64"))]
78    pub pmpcfg15: ReadWriteRiscvCsr<usize, pmpconfig::pmpcfg::Register, PMPCFG15>,
79
80    pub pmpaddr0: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR0>,
81    pub pmpaddr1: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR1>,
82    pub pmpaddr2: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR2>,
83    pub pmpaddr3: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR3>,
84    pub pmpaddr4: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR4>,
85    pub pmpaddr5: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR5>,
86    pub pmpaddr6: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR6>,
87    pub pmpaddr7: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR7>,
88    pub pmpaddr8: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR8>,
89    pub pmpaddr9: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR9>,
90    pub pmpaddr10: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR10>,
91    pub pmpaddr11: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR11>,
92    pub pmpaddr12: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR12>,
93    pub pmpaddr13: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR13>,
94    pub pmpaddr14: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR14>,
95    pub pmpaddr15: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR15>,
96    pub pmpaddr16: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR16>,
97    pub pmpaddr17: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR17>,
98    pub pmpaddr18: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR18>,
99    pub pmpaddr19: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR19>,
100    pub pmpaddr20: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR20>,
101    pub pmpaddr21: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR21>,
102    pub pmpaddr22: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR22>,
103    pub pmpaddr23: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR23>,
104    pub pmpaddr24: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR24>,
105    pub pmpaddr25: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR25>,
106    pub pmpaddr26: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR26>,
107    pub pmpaddr27: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR27>,
108    pub pmpaddr28: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR28>,
109    pub pmpaddr29: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR29>,
110    pub pmpaddr30: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR30>,
111    pub pmpaddr31: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR31>,
112    pub pmpaddr32: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR32>,
113    pub pmpaddr33: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR33>,
114    pub pmpaddr34: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR34>,
115    pub pmpaddr35: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR35>,
116    pub pmpaddr36: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR36>,
117    pub pmpaddr37: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR37>,
118    pub pmpaddr38: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR38>,
119    pub pmpaddr39: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR39>,
120    pub pmpaddr40: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR40>,
121    pub pmpaddr41: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR41>,
122    pub pmpaddr42: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR42>,
123    pub pmpaddr43: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR43>,
124    pub pmpaddr44: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR44>,
125    pub pmpaddr45: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR45>,
126    pub pmpaddr46: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR46>,
127    pub pmpaddr47: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR47>,
128    pub pmpaddr48: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR48>,
129    pub pmpaddr49: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR49>,
130    pub pmpaddr50: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR50>,
131    pub pmpaddr51: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR51>,
132    pub pmpaddr52: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR52>,
133    pub pmpaddr53: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR53>,
134    pub pmpaddr54: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR54>,
135    pub pmpaddr55: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR55>,
136    pub pmpaddr56: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR56>,
137    pub pmpaddr57: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR57>,
138    pub pmpaddr58: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR58>,
139    pub pmpaddr59: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR59>,
140    pub pmpaddr60: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR60>,
141    pub pmpaddr61: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR61>,
142    pub pmpaddr62: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR62>,
143    pub pmpaddr63: ReadWriteRiscvCsr<usize, pmpaddr::pmpaddr::Register, PMPADDR63>,
144
145    pub mie: ReadWriteRiscvCsr<usize, mie::mie::Register, MIE>,
146    pub mscratch: ReadWriteRiscvCsr<usize, mscratch::mscratch::Register, MSCRATCH>,
147    pub mepc: ReadWriteRiscvCsr<usize, mepc::mepc::Register, MEPC>,
148    pub mcause: ReadWriteRiscvCsr<usize, mcause::mcause::Register, MCAUSE>,
149    pub mtval: ReadWriteRiscvCsr<usize, mtval::mtval::Register, MTVAL>,
150    pub mip: ReadWriteRiscvCsr<usize, mip::mip::Register, MIP>,
151    pub mtvec: ReadWriteRiscvCsr<usize, mtvec::mtvec::Register, MTVEC>,
152    pub mstatus: ReadWriteRiscvCsr<usize, mstatus::mstatus::Register, MSTATUS>,
153
154    pub mseccfg: ReadWriteRiscvCsr<usize, mseccfg::mseccfg::Register, MSECCFG>,
155    #[cfg(not(target_arch = "riscv64"))]
156    pub mseccfgh: ReadWriteRiscvCsr<usize, mseccfg::mseccfgh::Register, MSECCFGH>,
157
158    pub utvec: ReadWriteRiscvCsr<usize, utvec::utvec::Register, UTVEC>,
159    pub stvec: ReadWriteRiscvCsr<usize, stvec::stvec::Register, STVEC>,
160}
161
162// Define the "addresses" of each CSR register.
163pub const CSR: &CSR = &CSR {
164    #[cfg(not(target_arch = "riscv64"))]
165    minstreth: ReadWriteRiscvCsr::new(),
166    minstret: ReadWriteRiscvCsr::new(),
167
168    #[cfg(not(target_arch = "riscv64"))]
169    mcycleh: ReadWriteRiscvCsr::new(),
170    mcycle: ReadWriteRiscvCsr::new(),
171
172    pmpcfg0: ReadWriteRiscvCsr::new(),
173    #[cfg(not(target_arch = "riscv64"))]
174    pmpcfg1: ReadWriteRiscvCsr::new(),
175    pmpcfg2: ReadWriteRiscvCsr::new(),
176    #[cfg(not(target_arch = "riscv64"))]
177    pmpcfg3: ReadWriteRiscvCsr::new(),
178    pmpcfg4: ReadWriteRiscvCsr::new(),
179    #[cfg(not(target_arch = "riscv64"))]
180    pmpcfg5: ReadWriteRiscvCsr::new(),
181    pmpcfg6: ReadWriteRiscvCsr::new(),
182    #[cfg(not(target_arch = "riscv64"))]
183    pmpcfg7: ReadWriteRiscvCsr::new(),
184    pmpcfg8: ReadWriteRiscvCsr::new(),
185    #[cfg(not(target_arch = "riscv64"))]
186    pmpcfg9: ReadWriteRiscvCsr::new(),
187    pmpcfg10: ReadWriteRiscvCsr::new(),
188    #[cfg(not(target_arch = "riscv64"))]
189    pmpcfg11: ReadWriteRiscvCsr::new(),
190    pmpcfg12: ReadWriteRiscvCsr::new(),
191    #[cfg(not(target_arch = "riscv64"))]
192    pmpcfg13: ReadWriteRiscvCsr::new(),
193    pmpcfg14: ReadWriteRiscvCsr::new(),
194    #[cfg(not(target_arch = "riscv64"))]
195    pmpcfg15: ReadWriteRiscvCsr::new(),
196
197    pmpaddr0: ReadWriteRiscvCsr::new(),
198    pmpaddr1: ReadWriteRiscvCsr::new(),
199    pmpaddr2: ReadWriteRiscvCsr::new(),
200    pmpaddr3: ReadWriteRiscvCsr::new(),
201    pmpaddr4: ReadWriteRiscvCsr::new(),
202    pmpaddr5: ReadWriteRiscvCsr::new(),
203    pmpaddr6: ReadWriteRiscvCsr::new(),
204    pmpaddr7: ReadWriteRiscvCsr::new(),
205    pmpaddr8: ReadWriteRiscvCsr::new(),
206    pmpaddr9: ReadWriteRiscvCsr::new(),
207    pmpaddr10: ReadWriteRiscvCsr::new(),
208    pmpaddr11: ReadWriteRiscvCsr::new(),
209    pmpaddr12: ReadWriteRiscvCsr::new(),
210    pmpaddr13: ReadWriteRiscvCsr::new(),
211    pmpaddr14: ReadWriteRiscvCsr::new(),
212    pmpaddr15: ReadWriteRiscvCsr::new(),
213    pmpaddr16: ReadWriteRiscvCsr::new(),
214    pmpaddr17: ReadWriteRiscvCsr::new(),
215    pmpaddr18: ReadWriteRiscvCsr::new(),
216    pmpaddr19: ReadWriteRiscvCsr::new(),
217    pmpaddr20: ReadWriteRiscvCsr::new(),
218    pmpaddr21: ReadWriteRiscvCsr::new(),
219    pmpaddr22: ReadWriteRiscvCsr::new(),
220    pmpaddr23: ReadWriteRiscvCsr::new(),
221    pmpaddr24: ReadWriteRiscvCsr::new(),
222    pmpaddr25: ReadWriteRiscvCsr::new(),
223    pmpaddr26: ReadWriteRiscvCsr::new(),
224    pmpaddr27: ReadWriteRiscvCsr::new(),
225    pmpaddr28: ReadWriteRiscvCsr::new(),
226    pmpaddr29: ReadWriteRiscvCsr::new(),
227    pmpaddr30: ReadWriteRiscvCsr::new(),
228    pmpaddr31: ReadWriteRiscvCsr::new(),
229    pmpaddr32: ReadWriteRiscvCsr::new(),
230    pmpaddr33: ReadWriteRiscvCsr::new(),
231    pmpaddr34: ReadWriteRiscvCsr::new(),
232    pmpaddr35: ReadWriteRiscvCsr::new(),
233    pmpaddr36: ReadWriteRiscvCsr::new(),
234    pmpaddr37: ReadWriteRiscvCsr::new(),
235    pmpaddr38: ReadWriteRiscvCsr::new(),
236    pmpaddr39: ReadWriteRiscvCsr::new(),
237    pmpaddr40: ReadWriteRiscvCsr::new(),
238    pmpaddr41: ReadWriteRiscvCsr::new(),
239    pmpaddr42: ReadWriteRiscvCsr::new(),
240    pmpaddr43: ReadWriteRiscvCsr::new(),
241    pmpaddr44: ReadWriteRiscvCsr::new(),
242    pmpaddr45: ReadWriteRiscvCsr::new(),
243    pmpaddr46: ReadWriteRiscvCsr::new(),
244    pmpaddr47: ReadWriteRiscvCsr::new(),
245    pmpaddr48: ReadWriteRiscvCsr::new(),
246    pmpaddr49: ReadWriteRiscvCsr::new(),
247    pmpaddr50: ReadWriteRiscvCsr::new(),
248    pmpaddr51: ReadWriteRiscvCsr::new(),
249    pmpaddr52: ReadWriteRiscvCsr::new(),
250    pmpaddr53: ReadWriteRiscvCsr::new(),
251    pmpaddr54: ReadWriteRiscvCsr::new(),
252    pmpaddr55: ReadWriteRiscvCsr::new(),
253    pmpaddr56: ReadWriteRiscvCsr::new(),
254    pmpaddr57: ReadWriteRiscvCsr::new(),
255    pmpaddr58: ReadWriteRiscvCsr::new(),
256    pmpaddr59: ReadWriteRiscvCsr::new(),
257    pmpaddr60: ReadWriteRiscvCsr::new(),
258    pmpaddr61: ReadWriteRiscvCsr::new(),
259    pmpaddr62: ReadWriteRiscvCsr::new(),
260    pmpaddr63: ReadWriteRiscvCsr::new(),
261
262    mie: ReadWriteRiscvCsr::new(),
263    mscratch: ReadWriteRiscvCsr::new(),
264    mepc: ReadWriteRiscvCsr::new(),
265    mcause: ReadWriteRiscvCsr::new(),
266    mtval: ReadWriteRiscvCsr::new(),
267    mip: ReadWriteRiscvCsr::new(),
268    mtvec: ReadWriteRiscvCsr::new(),
269    mstatus: ReadWriteRiscvCsr::new(),
270
271    mseccfg: ReadWriteRiscvCsr::new(),
272    #[cfg(not(target_arch = "riscv64"))]
273    mseccfgh: ReadWriteRiscvCsr::new(),
274
275    utvec: ReadWriteRiscvCsr::new(),
276    stvec: ReadWriteRiscvCsr::new(),
277};
278
279impl CSR {
280    // resets the cycle counter to 0
281    #[cfg(not(target_arch = "riscv64"))]
282    pub fn reset_cycle_counter(&self) {
283        // Write lower first so that we don't overflow before writing the upper
284        CSR.mcycle.write(mcycle::mcycle::mcycle.val(0));
285        CSR.mcycleh.write(mcycle::mcycleh::mcycleh.val(0));
286    }
287
288    // resets the cycle counter to 0
289    #[cfg(target_arch = "riscv64")]
290    pub fn reset_cycle_counter(&self) {
291        CSR.mcycle.write(mcycle::mcycle::mcycle.val(0));
292    }
293
294    // reads the cycle counter
295    #[cfg(not(target_arch = "riscv64"))]
296    pub fn read_cycle_counter(&self) -> u64 {
297        let (mut top, mut bot): (usize, usize);
298
299        // Need to handle the potential for rollover between reading the lower
300        // and upper bits. We do this by reading twice, and seeing if the upper
301        // bits change between reads. This should only ever loop at most twice.
302        loop {
303            top = CSR.mcycleh.read(mcycle::mcycleh::mcycleh);
304            bot = CSR.mcycle.read(mcycle::mcycle::mcycle);
305            if top == CSR.mcycleh.read(mcycle::mcycleh::mcycleh) {
306                break;
307            }
308        }
309
310        (top as u64).checked_shl(32).unwrap() + bot as u64
311    }
312
313    // reads the cycle counter
314    #[cfg(target_arch = "riscv64")]
315    pub fn read_cycle_counter(&self) -> u64 {
316        CSR.mcycle.read(mcycle::mcycle::mcycle)
317    }
318
319    pub fn pmpconfig_get(&self, index: usize) -> usize {
320        match index {
321            0 => self.pmpcfg0.get(),
322            #[cfg(not(target_arch = "riscv64"))]
323            1 => self.pmpcfg1.get(),
324            2 => self.pmpcfg2.get(),
325            #[cfg(not(target_arch = "riscv64"))]
326            3 => self.pmpcfg3.get(),
327            4 => self.pmpcfg4.get(),
328            #[cfg(not(target_arch = "riscv64"))]
329            5 => self.pmpcfg5.get(),
330            6 => self.pmpcfg6.get(),
331            #[cfg(not(target_arch = "riscv64"))]
332            7 => self.pmpcfg7.get(),
333            8 => self.pmpcfg8.get(),
334            #[cfg(not(target_arch = "riscv64"))]
335            9 => self.pmpcfg9.get(),
336            10 => self.pmpcfg10.get(),
337            #[cfg(not(target_arch = "riscv64"))]
338            11 => self.pmpcfg11.get(),
339            12 => self.pmpcfg12.get(),
340            #[cfg(not(target_arch = "riscv64"))]
341            13 => self.pmpcfg13.get(),
342            14 => self.pmpcfg14.get(),
343            #[cfg(not(target_arch = "riscv64"))]
344            15 => self.pmpcfg15.get(),
345            _ => unreachable!(),
346        }
347    }
348
349    pub fn pmpconfig_set(&self, index: usize, value: usize) {
350        match index {
351            0 => self.pmpcfg0.set(value),
352            #[cfg(not(target_arch = "riscv64"))]
353            1 => self.pmpcfg1.set(value),
354            2 => self.pmpcfg2.set(value),
355            #[cfg(not(target_arch = "riscv64"))]
356            3 => self.pmpcfg3.set(value),
357            4 => self.pmpcfg4.set(value),
358            #[cfg(not(target_arch = "riscv64"))]
359            5 => self.pmpcfg5.set(value),
360            6 => self.pmpcfg6.set(value),
361            #[cfg(not(target_arch = "riscv64"))]
362            7 => self.pmpcfg7.set(value),
363            8 => self.pmpcfg8.set(value),
364            #[cfg(not(target_arch = "riscv64"))]
365            9 => self.pmpcfg9.set(value),
366            10 => self.pmpcfg10.set(value),
367            #[cfg(not(target_arch = "riscv64"))]
368            11 => self.pmpcfg11.set(value),
369            12 => self.pmpcfg12.set(value),
370            #[cfg(not(target_arch = "riscv64"))]
371            13 => self.pmpcfg13.set(value),
372            14 => self.pmpcfg14.set(value),
373            #[cfg(not(target_arch = "riscv64"))]
374            15 => self.pmpcfg15.set(value),
375            _ => unreachable!(),
376        }
377    }
378
379    pub fn pmpconfig_modify(
380        &self,
381        index: usize,
382        field: FieldValue<usize, pmpconfig::pmpcfg::Register>,
383    ) {
384        match index {
385            0 => self.pmpcfg0.modify(field),
386            #[cfg(not(target_arch = "riscv64"))]
387            1 => self.pmpcfg1.modify(field),
388            2 => self.pmpcfg2.modify(field),
389            #[cfg(not(target_arch = "riscv64"))]
390            3 => self.pmpcfg3.modify(field),
391            4 => self.pmpcfg4.modify(field),
392            #[cfg(not(target_arch = "riscv64"))]
393            5 => self.pmpcfg5.modify(field),
394            6 => self.pmpcfg6.modify(field),
395            #[cfg(not(target_arch = "riscv64"))]
396            7 => self.pmpcfg7.modify(field),
397            8 => self.pmpcfg8.modify(field),
398            #[cfg(not(target_arch = "riscv64"))]
399            9 => self.pmpcfg9.modify(field),
400            10 => self.pmpcfg10.modify(field),
401            #[cfg(not(target_arch = "riscv64"))]
402            11 => self.pmpcfg11.modify(field),
403            12 => self.pmpcfg12.modify(field),
404            #[cfg(not(target_arch = "riscv64"))]
405            13 => self.pmpcfg13.modify(field),
406            14 => self.pmpcfg14.modify(field),
407            #[cfg(not(target_arch = "riscv64"))]
408            15 => self.pmpcfg15.modify(field),
409            _ => unreachable!(),
410        }
411    }
412
413    pub fn pmpaddr_set(&self, index: usize, value: usize) {
414        match index {
415            0 => self.pmpaddr0.set(value),
416            1 => self.pmpaddr1.set(value),
417            2 => self.pmpaddr2.set(value),
418            3 => self.pmpaddr3.set(value),
419            4 => self.pmpaddr4.set(value),
420            5 => self.pmpaddr5.set(value),
421            6 => self.pmpaddr6.set(value),
422            7 => self.pmpaddr7.set(value),
423            8 => self.pmpaddr8.set(value),
424            9 => self.pmpaddr9.set(value),
425            10 => self.pmpaddr10.set(value),
426            11 => self.pmpaddr11.set(value),
427            12 => self.pmpaddr12.set(value),
428            13 => self.pmpaddr13.set(value),
429            14 => self.pmpaddr14.set(value),
430            15 => self.pmpaddr15.set(value),
431            16 => self.pmpaddr16.set(value),
432            17 => self.pmpaddr17.set(value),
433            18 => self.pmpaddr18.set(value),
434            19 => self.pmpaddr19.set(value),
435            20 => self.pmpaddr20.set(value),
436            21 => self.pmpaddr21.set(value),
437            22 => self.pmpaddr22.set(value),
438            23 => self.pmpaddr23.set(value),
439            24 => self.pmpaddr24.set(value),
440            25 => self.pmpaddr25.set(value),
441            26 => self.pmpaddr26.set(value),
442            27 => self.pmpaddr27.set(value),
443            28 => self.pmpaddr28.set(value),
444            29 => self.pmpaddr29.set(value),
445            30 => self.pmpaddr30.set(value),
446            31 => self.pmpaddr31.set(value),
447            32 => self.pmpaddr32.set(value),
448            33 => self.pmpaddr33.set(value),
449            34 => self.pmpaddr34.set(value),
450            35 => self.pmpaddr35.set(value),
451            36 => self.pmpaddr36.set(value),
452            37 => self.pmpaddr37.set(value),
453            38 => self.pmpaddr38.set(value),
454            39 => self.pmpaddr39.set(value),
455            40 => self.pmpaddr40.set(value),
456            41 => self.pmpaddr41.set(value),
457            42 => self.pmpaddr42.set(value),
458            43 => self.pmpaddr43.set(value),
459            44 => self.pmpaddr44.set(value),
460            45 => self.pmpaddr45.set(value),
461            46 => self.pmpaddr46.set(value),
462            47 => self.pmpaddr47.set(value),
463            48 => self.pmpaddr48.set(value),
464            49 => self.pmpaddr49.set(value),
465            50 => self.pmpaddr50.set(value),
466            51 => self.pmpaddr51.set(value),
467            52 => self.pmpaddr52.set(value),
468            53 => self.pmpaddr53.set(value),
469            54 => self.pmpaddr54.set(value),
470            55 => self.pmpaddr55.set(value),
471            56 => self.pmpaddr56.set(value),
472            57 => self.pmpaddr57.set(value),
473            58 => self.pmpaddr58.set(value),
474            59 => self.pmpaddr59.set(value),
475            60 => self.pmpaddr60.set(value),
476            61 => self.pmpaddr61.set(value),
477            62 => self.pmpaddr62.set(value),
478            63 => self.pmpaddr63.set(value),
479            _ => unreachable!(),
480        }
481    }
482
483    pub fn pmpaddr_get(&self, index: usize) -> usize {
484        match index {
485            0 => self.pmpaddr0.get(),
486            1 => self.pmpaddr1.get(),
487            2 => self.pmpaddr2.get(),
488            3 => self.pmpaddr3.get(),
489            4 => self.pmpaddr4.get(),
490            5 => self.pmpaddr5.get(),
491            6 => self.pmpaddr6.get(),
492            7 => self.pmpaddr7.get(),
493            8 => self.pmpaddr8.get(),
494            9 => self.pmpaddr9.get(),
495            10 => self.pmpaddr10.get(),
496            11 => self.pmpaddr11.get(),
497            12 => self.pmpaddr12.get(),
498            13 => self.pmpaddr13.get(),
499            14 => self.pmpaddr14.get(),
500            15 => self.pmpaddr15.get(),
501            16 => self.pmpaddr16.get(),
502            17 => self.pmpaddr17.get(),
503            18 => self.pmpaddr18.get(),
504            19 => self.pmpaddr19.get(),
505            20 => self.pmpaddr20.get(),
506            21 => self.pmpaddr21.get(),
507            22 => self.pmpaddr22.get(),
508            23 => self.pmpaddr23.get(),
509            24 => self.pmpaddr24.get(),
510            25 => self.pmpaddr25.get(),
511            26 => self.pmpaddr26.get(),
512            27 => self.pmpaddr27.get(),
513            28 => self.pmpaddr28.get(),
514            29 => self.pmpaddr29.get(),
515            30 => self.pmpaddr30.get(),
516            31 => self.pmpaddr31.get(),
517            32 => self.pmpaddr32.get(),
518            33 => self.pmpaddr33.get(),
519            34 => self.pmpaddr34.get(),
520            35 => self.pmpaddr35.get(),
521            36 => self.pmpaddr36.get(),
522            37 => self.pmpaddr37.get(),
523            38 => self.pmpaddr38.get(),
524            39 => self.pmpaddr39.get(),
525            40 => self.pmpaddr40.get(),
526            41 => self.pmpaddr41.get(),
527            42 => self.pmpaddr42.get(),
528            43 => self.pmpaddr43.get(),
529            44 => self.pmpaddr44.get(),
530            45 => self.pmpaddr45.get(),
531            46 => self.pmpaddr46.get(),
532            47 => self.pmpaddr47.get(),
533            48 => self.pmpaddr48.get(),
534            49 => self.pmpaddr49.get(),
535            50 => self.pmpaddr50.get(),
536            51 => self.pmpaddr51.get(),
537            52 => self.pmpaddr52.get(),
538            53 => self.pmpaddr53.get(),
539            54 => self.pmpaddr54.get(),
540            55 => self.pmpaddr55.get(),
541            56 => self.pmpaddr56.get(),
542            57 => self.pmpaddr57.get(),
543            58 => self.pmpaddr58.get(),
544            59 => self.pmpaddr59.get(),
545            60 => self.pmpaddr60.get(),
546            61 => self.pmpaddr61.get(),
547            62 => self.pmpaddr62.get(),
548            63 => self.pmpaddr63.get(),
549            _ => unreachable!(),
550        }
551    }
552}
riscv/csr/mod.rs

riscv/csr/
mod.rs
