psoc62xa/
srss.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright OxidOS Automotive 2025 SRL.
4
5use kernel::utilities::registers::{
6    interfaces::ReadWriteable, register_bitfields, register_structs, ReadOnly, ReadWrite,
7};
8use kernel::utilities::StaticRef;
9
10register_structs! {
11    SrssRegisters {
12        (0x000 => pwr_ctl: ReadWrite<u32, PWR_CTL::Register>),
13        (0x004 => pwr_hibernate: ReadWrite<u32, PWR_HIBERNATE::Register>),
14        (0x008 => pwr_lvd_ctl: ReadWrite<u32, PWR_LVD_CTL::Register>),
15        (0x00C => _reserved0),
16        (0x014 => pwr_buck_ctl: ReadWrite<u32, PWR_BUCK_CTL::Register>),
17        (0x018 => _reserved17),
18        (0x01C => pwr_lvd_status: ReadOnly<u32>),
19        (0x020 => _reserved1),
20        (0x080 => pwr_hib_data_0: ReadWrite<u32>),
21        (0x084 => _reserved2),
22        (0x180 => wdt_ctl: ReadWrite<u32, WDT_CTL::Register>),
23        (0x184 => wdt_cnt: ReadWrite<u32>),
24        (0x188 => wdt_match: ReadWrite<u32, WDT_MATCH::Register>),
25        (0x18C => _reserved3),
26        (0x300 => clk_dsi_select_0: ReadWrite<u32>),
27        (0x304 => clk_dsi_select_1: ReadWrite<u32>),
28        (0x308 => clk_dsi_select_2: ReadWrite<u32>),
29        (0x30C => clk_dsi_select_3: ReadWrite<u32>),
30        (0x310 => clk_dsi_select_4: ReadWrite<u32>),
31        (0x314 => clk_dsi_select_5: ReadWrite<u32>),
32        (0x318 => _reserved18),
33        (0x340 => clk_path_select_0: ReadWrite<u32, CLK_PATH_SELECT0::Register>),
34        (0x344 => clk_path_select_1: ReadWrite<u32, CLK_PATH_SELECT1::Register>),
35        (0x348 => clk_path_select_2: ReadWrite<u32, CLK_PATH_SELECT2::Register>),
36        (0x34C => clk_path_select_3: ReadWrite<u32, CLK_PATH_SELECT3::Register>),
37        (0x350 => clk_path_select_4: ReadWrite<u32, CLK_PATH_SELECT4::Register>),
38        (0x354 => clk_path_select_5: ReadWrite<u32, CLK_PATH_SELECT5::Register>),
39        (0x358 => _reserved19),
40        (0x380 => clk_root_select_0: ReadWrite<u32, CLK_ROOT_SELECT0::Register>),
41        (0x384 => clk_root_select_1: ReadWrite<u32, CLK_ROOT_SELECT1::Register>),
42        (0x388 => clk_root_select_2: ReadWrite<u32, CLK_ROOT_SELECT2::Register>),
43        (0x38C => clk_root_select_3: ReadWrite<u32, CLK_ROOT_SELECT3::Register>),
44        (0x390 => clk_root_select_4: ReadWrite<u32, CLK_ROOT_SELECT4::Register>),
45        (0x394 => clk_root_select_5: ReadWrite<u32, CLK_ROOT_SELECT5::Register>),
46        (0x398 => _reserved4),
47        (0x500 => clk_select: ReadWrite<u32, CLK_SELECT::Register>),
48        (0x504 => clk_timer_ctl: ReadWrite<u32, CLK_TIMER_CTL::Register>),
49        (0x508 => _reserved5),
50        (0x50C => clk_ilo_config: ReadWrite<u32, CLK_ILO_CONFIG::Register>),
51        (0x510 => clk_imo_config: ReadWrite<u32>),
52        (0x514 => clk_output_fast: ReadWrite<u32, CLK_OUTPUT_FAST::Register>),
53        (0x518 => clk_output_slow: ReadWrite<u32, CLK_OUTPUT_SLOW::Register>),
54        (0x51C => clk_cal_cnt1: ReadWrite<u32, CLK_CAL_CNT1::Register>),
55        (0x520 => clk_cal_cnt2: ReadOnly<u32>),
56        (0x524 => _reserved6),
57        (0x52C => clk_eco_config: ReadWrite<u32, CLK_ECO_CONFIG::Register>),
58        (0x530 => clk_eco_status: ReadOnly<u32, CLK_ECO_STATUS::Register>),
59        (0x534 => _reserved7),
60        (0x53C => clk_pilo_config: ReadWrite<u32, CLK_PILO_CONFIG::Register>),
61        (0x540 => _reserved8),
62        (0x580 => clk_fll_config: ReadWrite<u32, CLK_FLL_CONFIG::Register>),
63        (0x584 => clk_fll_config2: ReadWrite<u32, CLK_FLL_CONFIG2::Register>),
64        (0x588 => clk_fll_config3: ReadWrite<u32, CLK_FLL_CONFIG3::Register>),
65        (0x58C => clk_fll_config4: ReadWrite<u32, CLK_FLL_CONFIG4::Register>),
66        (0x590 => clk_fll_status: ReadWrite<u32, CLK_FLL_STATUS::Register>),
67        (0x594 => _reserved9),
68        (0x600 => clk_pll_config_0: ReadWrite<u32, CLK_PLL_CONFIG0::Register>),
69        (0x604 => clk_pll_config_1: ReadWrite<u32, CLK_PLL_CONFIG1::Register>),
70        (0x608 => _reserved10),
71        (0x640 => clk_pll_status_0: ReadWrite<u32, CLK_PLL_STATUS0::Register>),
72        (0x644 => clk_pll_status_1: ReadWrite<u32, CLK_PLL_STATUS1::Register>),
73        (0x648 => _reserved11),
74        (0x700 => srss_intr: ReadWrite<u32, SRSS_INTR::Register>),
75        (0x704 => srss_intr_set: ReadWrite<u32, SRSS_INTR_SET::Register>),
76        (0x708 => srss_intr_mask: ReadWrite<u32, SRSS_INTR_MASK::Register>),
77        (0x70C => srss_intr_masked: ReadOnly<u32, SRSS_INTR_MASKED::Register>),
78        (0x710 => srss_intr_cfg: ReadWrite<u32>),
79        (0x714 => _reserved12),
80        (0x800 => res_cause: ReadWrite<u32, RES_CAUSE::Register>),
81        (0x804 => res_cause2: ReadWrite<u32, RES_CAUSE2::Register>),
82        (0x808 => _reserved13),
83        (0x7F00 => pwr_trim_ref_ctl: ReadWrite<u32, PWR_TRIM_REF_CTL::Register>),
84        (0x7F04 => pwr_trim_bodovp_ctl: ReadWrite<u32, PWR_TRIM_BODOVP_CTL::Register>),
85        (0x7F08 => clk_trim_cco_ctl: ReadWrite<u32, CLK_TRIM_CCO_CTL::Register>),
86        (0x7F0C => clk_trim_cco_ctl2: ReadWrite<u32, CLK_TRIM_CCO_CTL2::Register>),
87        (0x7F10 => _reserved14),
88        (0x7F30 => pwr_trim_wake_ctl: ReadWrite<u32>),
89        (0x7F34 => _reserved15),
90        (0xFF10 => pwr_trim_lvd_ctl: ReadWrite<u32, PWR_TRIM_LVD_CTL::Register>),
91        (0xFF14 => _reserved16),
92        (0xFF18 => clk_trim_ilo_ctl: ReadWrite<u32>),
93        (0xFF1C => pwr_trim_pwrsys_ctl: ReadWrite<u32, PWR_TRIM_PWRSYS_CTL::Register>),
94        (0xFF20 => clk_trim_eco_ctl: ReadWrite<u32, CLK_TRIM_ECO_CTL::Register>),
95        (0xFF24 => clk_trim_pilo_ctl: ReadWrite<u32, CLK_TRIM_PILO_CTL::Register>),
96        (0xFF28 => clk_trim_pilo_ctl2: ReadWrite<u32, CLK_TRIM_PILO_CTL2::Register>),
97        (0xFF2C => clk_trim_pilo_ctl3: ReadWrite<u32>),
98        (0xFF30 => @END),
99    }
100}
101register_bitfields![u32,
102PWR_CTL [
103    POWER_MODE OFFSET(0) NUMBITS(2) [
104        SystemIsResetting = 0,
105        AtLeastOneCPUIsRunning = 1,
106        NoCPUsAreRunningPeripheralsMayBeRunning = 2,
107        DEEPSLEEP = 3
108    ],
109    DEBUG_SESSION OFFSET(4) NUMBITS(1) [
110        NoDebugSessionActive = 0,
111        DebugSessionIsActivePowerModesBehaveDifferentlyToKeepTheDebugSessionActive = 1
112    ],
113    LPM_READY OFFSET(5) NUMBITS(1) [],
114    IREF_LPMODE OFFSET(18) NUMBITS(1) [],
115    VREFBUF_OK OFFSET(19) NUMBITS(1) [],
116    DPSLP_REG_DIS OFFSET(20) NUMBITS(1) [],
117    RET_REG_DIS OFFSET(21) NUMBITS(1) [],
118    NWELL_REG_DIS OFFSET(22) NUMBITS(1) [],
119    LINREG_DIS OFFSET(23) NUMBITS(1) [],
120    LINREG_LPMODE OFFSET(24) NUMBITS(1) [],
121    PORBOD_LPMODE OFFSET(25) NUMBITS(1) [],
122    BGREF_LPMODE OFFSET(26) NUMBITS(1) [],
123    PLL_LS_BYPASS OFFSET(27) NUMBITS(1) [],
124    VREFBUF_LPMODE OFFSET(28) NUMBITS(1) [],
125    VREFBUF_DIS OFFSET(29) NUMBITS(1) [],
126    ACT_REF_DIS OFFSET(30) NUMBITS(1) [],
127    ACT_REF_OK OFFSET(31) NUMBITS(1) []
128],
129PWR_HIBERNATE [
130    TOKEN OFFSET(0) NUMBITS(8) [],
131    UNLOCK OFFSET(8) NUMBITS(8) [],
132    FREEZE OFFSET(17) NUMBITS(1) [],
133    MASK_HIBALARM OFFSET(18) NUMBITS(1) [],
134    MASK_HIBWDT OFFSET(19) NUMBITS(1) [],
135    POLARITY_HIBPIN OFFSET(20) NUMBITS(4) [],
136    MASK_HIBPIN OFFSET(24) NUMBITS(4) [],
137    HIBERNATE_DISABLE OFFSET(30) NUMBITS(1) [],
138    HIBERNATE OFFSET(31) NUMBITS(1) []
139],
140PWR_LVD_CTL [
141    HVLVD1_TRIPSEL OFFSET(0) NUMBITS(4) [],
142    HVLVD1_SRCSEL OFFSET(4) NUMBITS(3) [
143        SelectVDDD = 0,
144        SelectAMUXBUSAVDDDBranch = 1,
145        NA = 2,
146        SelectAMUXBUSBVDDDBranch = 4
147    ],
148    HVLVD1_EN OFFSET(7) NUMBITS(1) []
149],
150PWR_BUCK_CTL [
151    BUCK_OUT1_SEL OFFSET(0) NUMBITS(3) [],
152    BUCK_EN OFFSET(30) NUMBITS(1) [],
153    BUCK_OUT1_EN OFFSET(31) NUMBITS(1) []
154],
155PWR_BUCK_CTL2 [
156    BUCK_OUT2_SEL OFFSET(0) NUMBITS(3) [],
157    BUCK_OUT2_HW_SEL OFFSET(30) NUMBITS(1) [],
158    BUCK_OUT2_EN OFFSET(31) NUMBITS(1) []
159],
160PWR_LVD_STATUS [
161    HVLVD1_OK OFFSET(0) NUMBITS(1) []
162],
163WDT_CTL [
164    WDT_EN OFFSET(0) NUMBITS(1) [],
165    WDT_LOCK OFFSET(30) NUMBITS(2) [
166        NoEffect = 0,
167        ClearsBit0 = 1,
168        ClearsBit1 = 2,
169        SetsBothBits0And1 = 3
170    ]
171],
172WDT_CNT [
173    COUNTER OFFSET(0) NUMBITS(16) []
174],
175WDT_MATCH [
176    MATCH OFFSET(0) NUMBITS(16) [],
177    IGNORE_BITS OFFSET(16) NUMBITS(4) []
178],
179CLK_SELECT [
180    LFCLK_SEL OFFSET(0) NUMBITS(2) [
181        ILOInternalLowSpeedOscillator = 0,
182        WCO = 1,
183        ALTLFAlternateLowFrequencyClockCapabilityIsProductSpecific = 2,
184        PILO = 3
185    ],
186    PUMP_SEL OFFSET(8) NUMBITS(4) [],
187    PUMP_DIV OFFSET(12) NUMBITS(3) [
188        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
189        DivideSelectedClockSourceBy2 = 1,
190        DivideSelectedClockSourceBy4 = 2,
191        DivideSelectedClockSourceBy8 = 3,
192        DivideSelectedClockSourceBy16 = 4
193    ],
194    PUMP_ENABLE OFFSET(15) NUMBITS(1) []
195],
196CLK_TIMER_CTL [
197    TIMER_SEL OFFSET(0) NUMBITS(1) [
198        IMOInternalMainOscillator = 0,
199        SelectTheOutputOfThePredividerConfiguredByTIMER_HF0_DIV = 1
200    ],
201    TIMER_HF0_DIV OFFSET(8) NUMBITS(2) [
202        TransparentModeFeedThroughSelectedClockSourceWODividingOrCorrectingDutyCycle = 0,
203        DivideHFCLK0By2 = 1,
204        DivideHFCLK0By4 = 2,
205        DivideHFCLK0By8 = 3
206    ],
207    TIMER_DIV OFFSET(16) NUMBITS(8) [],
208    ENABLE OFFSET(31) NUMBITS(1) []
209],
210CLK_ILO_CONFIG [
211    ILO_BACKUP OFFSET(0) NUMBITS(1) [],
212    ENABLE OFFSET(31) NUMBITS(1) []
213],
214CLK_IMO_CONFIG [
215    ENABLE OFFSET(31) NUMBITS(1) []
216],
217CLK_OUTPUT_FAST [
218    FAST_SEL0 OFFSET(0) NUMBITS(4) [
219        NC = 0,
220        ExternalCrystalOscillatorECO = 1,
221        ExternalClockInputEXTCLK = 2,
222        AlternateHighFrequencyALTHFClockInputToSRSS = 3,
223        TIMERCLK = 4,
224        SelectsTheClockPathChosenByPATH_SEL0Field = 5,
225        SelectsTheOutputOfTheHFCLK_SEL0Mux = 6,
226        SelectsTheOutputOfCLK_OUTPUT_SLOWSLOW_SEL0 = 7
227    ],
228    PATH_SEL0 OFFSET(4) NUMBITS(4) [],
229    HFCLK_SEL0 OFFSET(8) NUMBITS(4) [],
230    FAST_SEL1 OFFSET(16) NUMBITS(4) [
231        NC = 0,
232        ExternalCrystalOscillatorECO = 1,
233        ExternalClockInputEXTCLK = 2,
234        AlternateHighFrequencyALTHFClockInputToSRSS = 3,
235        TIMERCLK = 4,
236        SelectsTheClockPathChosenByPATH_SEL1Field = 5,
237        SelectsTheOutputOfTheHFCLK_SEL1Mux = 6,
238        SelectsTheOutputOfCLK_OUTPUT_SLOWSLOW_SEL1 = 7
239    ],
240    PATH_SEL1 OFFSET(20) NUMBITS(4) [],
241    HFCLK_SEL1 OFFSET(24) NUMBITS(4) []
242],
243CLK_OUTPUT_SLOW [
244    SLOW_SEL0 OFFSET(0) NUMBITS(4) [
245        DisabledOutputIs0ForPowerSavingsClocksAreBlockedBeforeEnteringAnyMuxes = 0,
246        InternalLowSpeedOscillatorILO = 1,
247        WatchCrystalOscillatorWCO = 2,
248        RootOfTheBackupDomainClockTreeBAK = 3,
249        AlternateLowFrequencyClockInputToSRSSALTLF = 4,
250        RootOfTheLowSpeedClockTreeLFCLK = 5,
251        IMO = 6,
252        SLPCTRL = 7,
253        PrecisionInternalLowSpeedOscillatorPILO = 8
254    ],
255    SLOW_SEL1 OFFSET(4) NUMBITS(4) [
256        DisabledOutputIs0ForPowerSavingsClocksAreBlockedBeforeEnteringAnyMuxes = 0,
257        InternalLowSpeedOscillatorILO = 1,
258        WatchCrystalOscillatorWCO = 2,
259        RootOfTheBackupDomainClockTreeBAK = 3,
260        AlternateLowFrequencyClockInputToSRSSALTLF = 4,
261        RootOfTheLowSpeedClockTreeLFCLK = 5,
262        IMO = 6,
263        SLPCTRL = 7,
264        PrecisionInternalLowSpeedOscillatorPILO = 8
265    ]
266],
267CLK_CAL_CNT1 [
268    CAL_COUNTER1 OFFSET(0) NUMBITS(24) [],
269    CAL_COUNTER_DONE OFFSET(31) NUMBITS(1) []
270],
271CLK_CAL_CNT2 [
272    CAL_COUNTER2 OFFSET(0) NUMBITS(24) []
273],
274CLK_ECO_CONFIG [
275    AGC_EN OFFSET(1) NUMBITS(1) [],
276    ECO_EN OFFSET(31) NUMBITS(1) []
277],
278CLK_ECO_STATUS [
279    ECO_OK OFFSET(0) NUMBITS(1) [],
280    ECO_READY OFFSET(1) NUMBITS(1) []
281],
282CLK_PILO_CONFIG [
283    PILO_FFREQ OFFSET(0) NUMBITS(10) [],
284    PILO_CLK_EN OFFSET(29) NUMBITS(1) [],
285    PILO_RESET_N OFFSET(30) NUMBITS(1) [],
286    PILO_EN OFFSET(31) NUMBITS(1) []
287],
288CLK_FLL_CONFIG [
289    FLL_MULT OFFSET(0) NUMBITS(18) [],
290    FLL_OUTPUT_DIV OFFSET(24) NUMBITS(1) [],
291    FLL_ENABLE OFFSET(31) NUMBITS(1) []
292],
293CLK_FLL_CONFIG2 [
294    FLL_REF_DIV OFFSET(0) NUMBITS(13) [],
295    LOCK_TOL OFFSET(16) NUMBITS(9) []
296],
297CLK_FLL_CONFIG3 [
298    FLL_LF_IGAIN OFFSET(0) NUMBITS(4) [],
299    FLL_LF_PGAIN OFFSET(4) NUMBITS(4) [],
300    SETTLING_COUNT OFFSET(8) NUMBITS(13) [],
301    BYPASS_SEL OFFSET(28) NUMBITS(2) [
302        NA = 0,
303        SelectFLLReferenceInputBypassModeIgnoresLockIndicator = 2,
304        SelectFLLOutputIgnoresLockIndicator = 3
305    ]
306],
307CLK_FLL_CONFIG4 [
308    CCO_LIMIT OFFSET(0) NUMBITS(8) [],
309    CCO_RANGE OFFSET(8) NUMBITS(3) [
310        TargetFrequencyIsInRange4864MHz = 0,
311        TargetFrequencyIsInRange6485MHz = 1,
312        TargetFrequencyIsInRange85113MHz = 2,
313        TargetFrequencyIsInRange113150MHz = 3,
314        TargetFrequencyIsInRange150200MHz = 4
315    ],
316    CCO_FREQ OFFSET(16) NUMBITS(9) [],
317    CCO_HW_UPDATE_DIS OFFSET(30) NUMBITS(1) [],
318    CCO_ENABLE OFFSET(31) NUMBITS(1) []
319],
320CLK_FLL_STATUS [
321    LOCKED OFFSET(0) NUMBITS(1) [],
322    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) [],
323    CCO_READY OFFSET(2) NUMBITS(1) []
324],
325SRSS_INTR [
326    WDT_MATCH OFFSET(0) NUMBITS(1) [],
327    HVLVD1 OFFSET(1) NUMBITS(1) [],
328    CLK_CAL OFFSET(5) NUMBITS(1) []
329],
330SRSS_INTR_SET [
331    WDT_MATCH OFFSET(0) NUMBITS(1) [],
332    HVLVD1 OFFSET(1) NUMBITS(1) [],
333    CLK_CAL OFFSET(5) NUMBITS(1) []
334],
335SRSS_INTR_MASK [
336    WDT_MATCH OFFSET(0) NUMBITS(1) [],
337    HVLVD1 OFFSET(1) NUMBITS(1) [],
338    CLK_CAL OFFSET(5) NUMBITS(1) []
339],
340SRSS_INTR_MASKED [
341    WDT_MATCH OFFSET(0) NUMBITS(1) [],
342    HVLVD1 OFFSET(1) NUMBITS(1) [],
343    CLK_CAL OFFSET(5) NUMBITS(1) []
344],
345SRSS_INTR_CFG [
346    HVLVD1_EDGE_SEL OFFSET(0) NUMBITS(2) [
347        Disabled = 0,
348        RisingEdge = 1,
349        FallingEdge = 2,
350        BothRisingAndFallingEdges = 3
351    ]
352],
353RES_CAUSE [
354    RESET_WDT OFFSET(0) NUMBITS(1) [],
355    RESET_ACT_FAULT OFFSET(1) NUMBITS(1) [],
356    RESET_DPSLP_FAULT OFFSET(2) NUMBITS(1) [],
357    RESET_CSV_WCO_LOSS OFFSET(3) NUMBITS(1) [],
358    RESET_SOFT OFFSET(4) NUMBITS(1) [],
359    RESET_MCWDT0 OFFSET(5) NUMBITS(1) [],
360    RESET_MCWDT1 OFFSET(6) NUMBITS(1) [],
361    RESET_MCWDT2 OFFSET(7) NUMBITS(1) [],
362    RESET_MCWDT3 OFFSET(8) NUMBITS(1) []
363],
364RES_CAUSE2 [
365    RESET_CSV_HF_LOSS OFFSET(0) NUMBITS(16) [],
366    RESET_CSV_HF_FREQ OFFSET(16) NUMBITS(16) []
367],
368PWR_TRIM_REF_CTL [
369    ACT_REF_TCTRIM OFFSET(0) NUMBITS(4) [],
370    ACT_REF_ITRIM OFFSET(4) NUMBITS(4) [],
371    ACT_REF_ABSTRIM OFFSET(8) NUMBITS(5) [],
372    ACT_REF_IBOOST OFFSET(14) NUMBITS(1) [],
373    DPSLP_REF_TCTRIM OFFSET(16) NUMBITS(4) [],
374    DPSLP_REF_ABSTRIM OFFSET(20) NUMBITS(5) [],
375    DPSLP_REF_ITRIM OFFSET(28) NUMBITS(4) []
376],
377PWR_TRIM_BODOVP_CTL [
378    HVPORBOD_TRIPSEL OFFSET(0) NUMBITS(3) [],
379    HVPORBOD_OFSTRIM OFFSET(4) NUMBITS(3) [],
380    HVPORBOD_ITRIM OFFSET(7) NUMBITS(3) [],
381    LVPORBOD_TRIPSEL OFFSET(10) NUMBITS(3) [],
382    LVPORBOD_OFSTRIM OFFSET(14) NUMBITS(3) [],
383    LVPORBOD_ITRIM OFFSET(17) NUMBITS(3) []
384],
385CLK_TRIM_CCO_CTL [
386    CCO_RCSTRIM OFFSET(0) NUMBITS(6) [],
387    CCO_STABLE_CNT OFFSET(24) NUMBITS(6) [],
388    ENABLE_CNT OFFSET(31) NUMBITS(1) []
389],
390CLK_TRIM_CCO_CTL2 [
391    CCO_FCTRIM1 OFFSET(0) NUMBITS(5) [],
392    CCO_FCTRIM2 OFFSET(5) NUMBITS(5) [],
393    CCO_FCTRIM3 OFFSET(10) NUMBITS(5) [],
394    CCO_FCTRIM4 OFFSET(15) NUMBITS(5) [],
395    CCO_FCTRIM5 OFFSET(20) NUMBITS(5) []
396],
397PWR_TRIM_WAKE_CTL [
398    WAKE_DELAY OFFSET(0) NUMBITS(8) []
399],
400PWR_TRIM_LVD_CTL [
401    HVLVD1_OFSTRIM OFFSET(0) NUMBITS(3) [],
402    HVLVD1_ITRIM OFFSET(4) NUMBITS(3) []
403],
404CLK_TRIM_ILO_CTL [
405    ILO_FTRIM OFFSET(0) NUMBITS(6) []
406],
407PWR_TRIM_PWRSYS_CTL [
408    ACT_REG_TRIM OFFSET(0) NUMBITS(5) [],
409    ACT_REG_BOOST OFFSET(30) NUMBITS(2) []
410],
411CLK_TRIM_ECO_CTL [
412    WDTRIM OFFSET(0) NUMBITS(3) [],
413    ATRIM OFFSET(4) NUMBITS(4) [],
414    FTRIM OFFSET(8) NUMBITS(2) [],
415    RTRIM OFFSET(10) NUMBITS(2) [],
416    GTRIM OFFSET(12) NUMBITS(2) [],
417    ITRIM OFFSET(16) NUMBITS(6) []
418],
419CLK_TRIM_PILO_CTL [
420    PILO_CFREQ OFFSET(0) NUMBITS(6) [],
421    PILO_OSC_TRIM OFFSET(12) NUMBITS(3) [],
422    PILO_COMP_TRIM OFFSET(16) NUMBITS(2) [],
423    PILO_NBIAS_TRIM OFFSET(18) NUMBITS(2) [],
424    PILO_RES_TRIM OFFSET(20) NUMBITS(5) [],
425    PILO_ISLOPE_TRIM OFFSET(26) NUMBITS(2) [],
426    PILO_VTDIFF_TRIM OFFSET(28) NUMBITS(3) []
427],
428CLK_TRIM_PILO_CTL2 [
429    PILO_VREF_TRIM OFFSET(0) NUMBITS(8) [],
430    PILO_IREFBM_TRIM OFFSET(8) NUMBITS(5) [],
431    PILO_IREF_TRIM OFFSET(16) NUMBITS(8) []
432],
433CLK_TRIM_PILO_CTL3 [
434    PILO_ENGOPT OFFSET(0) NUMBITS(16) []
435],
436PWR_HIB_DATA0 [
437    HIB_DATA OFFSET(0) NUMBITS(32) []
438],
439PWR_HIB_DATA1 [
440    HIB_DATA OFFSET(0) NUMBITS(32) []
441],
442PWR_HIB_DATA2 [
443    HIB_DATA OFFSET(0) NUMBITS(32) []
444],
445PWR_HIB_DATA3 [
446    HIB_DATA OFFSET(0) NUMBITS(32) []
447],
448PWR_HIB_DATA4 [
449    HIB_DATA OFFSET(0) NUMBITS(32) []
450],
451PWR_HIB_DATA5 [
452    HIB_DATA OFFSET(0) NUMBITS(32) []
453],
454PWR_HIB_DATA6 [
455    HIB_DATA OFFSET(0) NUMBITS(32) []
456],
457PWR_HIB_DATA7 [
458    HIB_DATA OFFSET(0) NUMBITS(32) []
459],
460PWR_HIB_DATA8 [
461    HIB_DATA OFFSET(0) NUMBITS(32) []
462],
463PWR_HIB_DATA9 [
464    HIB_DATA OFFSET(0) NUMBITS(32) []
465],
466PWR_HIB_DATA10 [
467    HIB_DATA OFFSET(0) NUMBITS(32) []
468],
469PWR_HIB_DATA11 [
470    HIB_DATA OFFSET(0) NUMBITS(32) []
471],
472PWR_HIB_DATA12 [
473    HIB_DATA OFFSET(0) NUMBITS(32) []
474],
475PWR_HIB_DATA13 [
476    HIB_DATA OFFSET(0) NUMBITS(32) []
477],
478PWR_HIB_DATA14 [
479    HIB_DATA OFFSET(0) NUMBITS(32) []
480],
481PWR_HIB_DATA15 [
482    HIB_DATA OFFSET(0) NUMBITS(32) []
483],
484CLK_DSI_SELECT0 [
485    DSI_MUX OFFSET(0) NUMBITS(5) [
486        DSI0Dsi_out0 = 0,
487        DSI1Dsi_out1 = 1,
488        DSI2Dsi_out2 = 2,
489        DSI3Dsi_out3 = 3,
490        DSI4Dsi_out4 = 4,
491        DSI5Dsi_out5 = 5,
492        DSI6Dsi_out6 = 6,
493        DSI7Dsi_out7 = 7,
494        DSI8Dsi_out8 = 8,
495        DSI9Dsi_out9 = 9,
496        DSI10Dsi_out10 = 10,
497        DSI11Dsi_out11 = 11,
498        DSI12Dsi_out12 = 12,
499        DSI13Dsi_out13 = 13,
500        DSI14Dsi_out14 = 14,
501        DSI15Dsi_out15 = 15,
502        ILOInternalLowSpeedOscillator = 16,
503        WCOWatchCrystalOscillator = 17,
504        ALTLFAlternateLowFrequencyClock = 18,
505        PILOPrecisionInternalLowSpeedOscillator = 19
506    ]
507],
508CLK_DSI_SELECT1 [
509    DSI_MUX OFFSET(0) NUMBITS(5) [
510        DSI0Dsi_out0 = 0,
511        DSI1Dsi_out1 = 1,
512        DSI2Dsi_out2 = 2,
513        DSI3Dsi_out3 = 3,
514        DSI4Dsi_out4 = 4,
515        DSI5Dsi_out5 = 5,
516        DSI6Dsi_out6 = 6,
517        DSI7Dsi_out7 = 7,
518        DSI8Dsi_out8 = 8,
519        DSI9Dsi_out9 = 9,
520        DSI10Dsi_out10 = 10,
521        DSI11Dsi_out11 = 11,
522        DSI12Dsi_out12 = 12,
523        DSI13Dsi_out13 = 13,
524        DSI14Dsi_out14 = 14,
525        DSI15Dsi_out15 = 15,
526        ILOInternalLowSpeedOscillator = 16,
527        WCOWatchCrystalOscillator = 17,
528        ALTLFAlternateLowFrequencyClock = 18,
529        PILOPrecisionInternalLowSpeedOscillator = 19
530    ]
531],
532CLK_DSI_SELECT2 [
533    DSI_MUX OFFSET(0) NUMBITS(5) [
534        DSI0Dsi_out0 = 0,
535        DSI1Dsi_out1 = 1,
536        DSI2Dsi_out2 = 2,
537        DSI3Dsi_out3 = 3,
538        DSI4Dsi_out4 = 4,
539        DSI5Dsi_out5 = 5,
540        DSI6Dsi_out6 = 6,
541        DSI7Dsi_out7 = 7,
542        DSI8Dsi_out8 = 8,
543        DSI9Dsi_out9 = 9,
544        DSI10Dsi_out10 = 10,
545        DSI11Dsi_out11 = 11,
546        DSI12Dsi_out12 = 12,
547        DSI13Dsi_out13 = 13,
548        DSI14Dsi_out14 = 14,
549        DSI15Dsi_out15 = 15,
550        ILOInternalLowSpeedOscillator = 16,
551        WCOWatchCrystalOscillator = 17,
552        ALTLFAlternateLowFrequencyClock = 18,
553        PILOPrecisionInternalLowSpeedOscillator = 19
554    ]
555],
556CLK_DSI_SELECT3 [
557    DSI_MUX OFFSET(0) NUMBITS(5) [
558        DSI0Dsi_out0 = 0,
559        DSI1Dsi_out1 = 1,
560        DSI2Dsi_out2 = 2,
561        DSI3Dsi_out3 = 3,
562        DSI4Dsi_out4 = 4,
563        DSI5Dsi_out5 = 5,
564        DSI6Dsi_out6 = 6,
565        DSI7Dsi_out7 = 7,
566        DSI8Dsi_out8 = 8,
567        DSI9Dsi_out9 = 9,
568        DSI10Dsi_out10 = 10,
569        DSI11Dsi_out11 = 11,
570        DSI12Dsi_out12 = 12,
571        DSI13Dsi_out13 = 13,
572        DSI14Dsi_out14 = 14,
573        DSI15Dsi_out15 = 15,
574        ILOInternalLowSpeedOscillator = 16,
575        WCOWatchCrystalOscillator = 17,
576        ALTLFAlternateLowFrequencyClock = 18,
577        PILOPrecisionInternalLowSpeedOscillator = 19
578    ]
579],
580CLK_DSI_SELECT4 [
581    DSI_MUX OFFSET(0) NUMBITS(5) [
582        DSI0Dsi_out0 = 0,
583        DSI1Dsi_out1 = 1,
584        DSI2Dsi_out2 = 2,
585        DSI3Dsi_out3 = 3,
586        DSI4Dsi_out4 = 4,
587        DSI5Dsi_out5 = 5,
588        DSI6Dsi_out6 = 6,
589        DSI7Dsi_out7 = 7,
590        DSI8Dsi_out8 = 8,
591        DSI9Dsi_out9 = 9,
592        DSI10Dsi_out10 = 10,
593        DSI11Dsi_out11 = 11,
594        DSI12Dsi_out12 = 12,
595        DSI13Dsi_out13 = 13,
596        DSI14Dsi_out14 = 14,
597        DSI15Dsi_out15 = 15,
598        ILOInternalLowSpeedOscillator = 16,
599        WCOWatchCrystalOscillator = 17,
600        ALTLFAlternateLowFrequencyClock = 18,
601        PILOPrecisionInternalLowSpeedOscillator = 19
602    ]
603],
604CLK_DSI_SELECT5 [
605    DSI_MUX OFFSET(0) NUMBITS(5) [
606        DSI0Dsi_out0 = 0,
607        DSI1Dsi_out1 = 1,
608        DSI2Dsi_out2 = 2,
609        DSI3Dsi_out3 = 3,
610        DSI4Dsi_out4 = 4,
611        DSI5Dsi_out5 = 5,
612        DSI6Dsi_out6 = 6,
613        DSI7Dsi_out7 = 7,
614        DSI8Dsi_out8 = 8,
615        DSI9Dsi_out9 = 9,
616        DSI10Dsi_out10 = 10,
617        DSI11Dsi_out11 = 11,
618        DSI12Dsi_out12 = 12,
619        DSI13Dsi_out13 = 13,
620        DSI14Dsi_out14 = 14,
621        DSI15Dsi_out15 = 15,
622        ILOInternalLowSpeedOscillator = 16,
623        WCOWatchCrystalOscillator = 17,
624        ALTLFAlternateLowFrequencyClock = 18,
625        PILOPrecisionInternalLowSpeedOscillator = 19
626    ]
627],
628CLK_DSI_SELECT6 [
629    DSI_MUX OFFSET(0) NUMBITS(5) [
630        DSI0Dsi_out0 = 0,
631        DSI1Dsi_out1 = 1,
632        DSI2Dsi_out2 = 2,
633        DSI3Dsi_out3 = 3,
634        DSI4Dsi_out4 = 4,
635        DSI5Dsi_out5 = 5,
636        DSI6Dsi_out6 = 6,
637        DSI7Dsi_out7 = 7,
638        DSI8Dsi_out8 = 8,
639        DSI9Dsi_out9 = 9,
640        DSI10Dsi_out10 = 10,
641        DSI11Dsi_out11 = 11,
642        DSI12Dsi_out12 = 12,
643        DSI13Dsi_out13 = 13,
644        DSI14Dsi_out14 = 14,
645        DSI15Dsi_out15 = 15,
646        ILOInternalLowSpeedOscillator = 16,
647        WCOWatchCrystalOscillator = 17,
648        ALTLFAlternateLowFrequencyClock = 18,
649        PILOPrecisionInternalLowSpeedOscillator = 19
650    ]
651],
652CLK_DSI_SELECT7 [
653    DSI_MUX OFFSET(0) NUMBITS(5) [
654        DSI0Dsi_out0 = 0,
655        DSI1Dsi_out1 = 1,
656        DSI2Dsi_out2 = 2,
657        DSI3Dsi_out3 = 3,
658        DSI4Dsi_out4 = 4,
659        DSI5Dsi_out5 = 5,
660        DSI6Dsi_out6 = 6,
661        DSI7Dsi_out7 = 7,
662        DSI8Dsi_out8 = 8,
663        DSI9Dsi_out9 = 9,
664        DSI10Dsi_out10 = 10,
665        DSI11Dsi_out11 = 11,
666        DSI12Dsi_out12 = 12,
667        DSI13Dsi_out13 = 13,
668        DSI14Dsi_out14 = 14,
669        DSI15Dsi_out15 = 15,
670        ILOInternalLowSpeedOscillator = 16,
671        WCOWatchCrystalOscillator = 17,
672        ALTLFAlternateLowFrequencyClock = 18,
673        PILOPrecisionInternalLowSpeedOscillator = 19
674    ]
675],
676CLK_DSI_SELECT8 [
677    DSI_MUX OFFSET(0) NUMBITS(5) [
678        DSI0Dsi_out0 = 0,
679        DSI1Dsi_out1 = 1,
680        DSI2Dsi_out2 = 2,
681        DSI3Dsi_out3 = 3,
682        DSI4Dsi_out4 = 4,
683        DSI5Dsi_out5 = 5,
684        DSI6Dsi_out6 = 6,
685        DSI7Dsi_out7 = 7,
686        DSI8Dsi_out8 = 8,
687        DSI9Dsi_out9 = 9,
688        DSI10Dsi_out10 = 10,
689        DSI11Dsi_out11 = 11,
690        DSI12Dsi_out12 = 12,
691        DSI13Dsi_out13 = 13,
692        DSI14Dsi_out14 = 14,
693        DSI15Dsi_out15 = 15,
694        ILOInternalLowSpeedOscillator = 16,
695        WCOWatchCrystalOscillator = 17,
696        ALTLFAlternateLowFrequencyClock = 18,
697        PILOPrecisionInternalLowSpeedOscillator = 19
698    ]
699],
700CLK_DSI_SELECT9 [
701    DSI_MUX OFFSET(0) NUMBITS(5) [
702        DSI0Dsi_out0 = 0,
703        DSI1Dsi_out1 = 1,
704        DSI2Dsi_out2 = 2,
705        DSI3Dsi_out3 = 3,
706        DSI4Dsi_out4 = 4,
707        DSI5Dsi_out5 = 5,
708        DSI6Dsi_out6 = 6,
709        DSI7Dsi_out7 = 7,
710        DSI8Dsi_out8 = 8,
711        DSI9Dsi_out9 = 9,
712        DSI10Dsi_out10 = 10,
713        DSI11Dsi_out11 = 11,
714        DSI12Dsi_out12 = 12,
715        DSI13Dsi_out13 = 13,
716        DSI14Dsi_out14 = 14,
717        DSI15Dsi_out15 = 15,
718        ILOInternalLowSpeedOscillator = 16,
719        WCOWatchCrystalOscillator = 17,
720        ALTLFAlternateLowFrequencyClock = 18,
721        PILOPrecisionInternalLowSpeedOscillator = 19
722    ]
723],
724CLK_DSI_SELECT10 [
725    DSI_MUX OFFSET(0) NUMBITS(5) [
726        DSI0Dsi_out0 = 0,
727        DSI1Dsi_out1 = 1,
728        DSI2Dsi_out2 = 2,
729        DSI3Dsi_out3 = 3,
730        DSI4Dsi_out4 = 4,
731        DSI5Dsi_out5 = 5,
732        DSI6Dsi_out6 = 6,
733        DSI7Dsi_out7 = 7,
734        DSI8Dsi_out8 = 8,
735        DSI9Dsi_out9 = 9,
736        DSI10Dsi_out10 = 10,
737        DSI11Dsi_out11 = 11,
738        DSI12Dsi_out12 = 12,
739        DSI13Dsi_out13 = 13,
740        DSI14Dsi_out14 = 14,
741        DSI15Dsi_out15 = 15,
742        ILOInternalLowSpeedOscillator = 16,
743        WCOWatchCrystalOscillator = 17,
744        ALTLFAlternateLowFrequencyClock = 18,
745        PILOPrecisionInternalLowSpeedOscillator = 19
746    ]
747],
748CLK_DSI_SELECT11 [
749    DSI_MUX OFFSET(0) NUMBITS(5) [
750        DSI0Dsi_out0 = 0,
751        DSI1Dsi_out1 = 1,
752        DSI2Dsi_out2 = 2,
753        DSI3Dsi_out3 = 3,
754        DSI4Dsi_out4 = 4,
755        DSI5Dsi_out5 = 5,
756        DSI6Dsi_out6 = 6,
757        DSI7Dsi_out7 = 7,
758        DSI8Dsi_out8 = 8,
759        DSI9Dsi_out9 = 9,
760        DSI10Dsi_out10 = 10,
761        DSI11Dsi_out11 = 11,
762        DSI12Dsi_out12 = 12,
763        DSI13Dsi_out13 = 13,
764        DSI14Dsi_out14 = 14,
765        DSI15Dsi_out15 = 15,
766        ILOInternalLowSpeedOscillator = 16,
767        WCOWatchCrystalOscillator = 17,
768        ALTLFAlternateLowFrequencyClock = 18,
769        PILOPrecisionInternalLowSpeedOscillator = 19
770    ]
771],
772CLK_DSI_SELECT12 [
773    DSI_MUX OFFSET(0) NUMBITS(5) [
774        DSI0Dsi_out0 = 0,
775        DSI1Dsi_out1 = 1,
776        DSI2Dsi_out2 = 2,
777        DSI3Dsi_out3 = 3,
778        DSI4Dsi_out4 = 4,
779        DSI5Dsi_out5 = 5,
780        DSI6Dsi_out6 = 6,
781        DSI7Dsi_out7 = 7,
782        DSI8Dsi_out8 = 8,
783        DSI9Dsi_out9 = 9,
784        DSI10Dsi_out10 = 10,
785        DSI11Dsi_out11 = 11,
786        DSI12Dsi_out12 = 12,
787        DSI13Dsi_out13 = 13,
788        DSI14Dsi_out14 = 14,
789        DSI15Dsi_out15 = 15,
790        ILOInternalLowSpeedOscillator = 16,
791        WCOWatchCrystalOscillator = 17,
792        ALTLFAlternateLowFrequencyClock = 18,
793        PILOPrecisionInternalLowSpeedOscillator = 19
794    ]
795],
796CLK_DSI_SELECT13 [
797    DSI_MUX OFFSET(0) NUMBITS(5) [
798        DSI0Dsi_out0 = 0,
799        DSI1Dsi_out1 = 1,
800        DSI2Dsi_out2 = 2,
801        DSI3Dsi_out3 = 3,
802        DSI4Dsi_out4 = 4,
803        DSI5Dsi_out5 = 5,
804        DSI6Dsi_out6 = 6,
805        DSI7Dsi_out7 = 7,
806        DSI8Dsi_out8 = 8,
807        DSI9Dsi_out9 = 9,
808        DSI10Dsi_out10 = 10,
809        DSI11Dsi_out11 = 11,
810        DSI12Dsi_out12 = 12,
811        DSI13Dsi_out13 = 13,
812        DSI14Dsi_out14 = 14,
813        DSI15Dsi_out15 = 15,
814        ILOInternalLowSpeedOscillator = 16,
815        WCOWatchCrystalOscillator = 17,
816        ALTLFAlternateLowFrequencyClock = 18,
817        PILOPrecisionInternalLowSpeedOscillator = 19
818    ]
819],
820CLK_DSI_SELECT14 [
821    DSI_MUX OFFSET(0) NUMBITS(5) [
822        DSI0Dsi_out0 = 0,
823        DSI1Dsi_out1 = 1,
824        DSI2Dsi_out2 = 2,
825        DSI3Dsi_out3 = 3,
826        DSI4Dsi_out4 = 4,
827        DSI5Dsi_out5 = 5,
828        DSI6Dsi_out6 = 6,
829        DSI7Dsi_out7 = 7,
830        DSI8Dsi_out8 = 8,
831        DSI9Dsi_out9 = 9,
832        DSI10Dsi_out10 = 10,
833        DSI11Dsi_out11 = 11,
834        DSI12Dsi_out12 = 12,
835        DSI13Dsi_out13 = 13,
836        DSI14Dsi_out14 = 14,
837        DSI15Dsi_out15 = 15,
838        ILOInternalLowSpeedOscillator = 16,
839        WCOWatchCrystalOscillator = 17,
840        ALTLFAlternateLowFrequencyClock = 18,
841        PILOPrecisionInternalLowSpeedOscillator = 19
842    ]
843],
844CLK_DSI_SELECT15 [
845    DSI_MUX OFFSET(0) NUMBITS(5) [
846        DSI0Dsi_out0 = 0,
847        DSI1Dsi_out1 = 1,
848        DSI2Dsi_out2 = 2,
849        DSI3Dsi_out3 = 3,
850        DSI4Dsi_out4 = 4,
851        DSI5Dsi_out5 = 5,
852        DSI6Dsi_out6 = 6,
853        DSI7Dsi_out7 = 7,
854        DSI8Dsi_out8 = 8,
855        DSI9Dsi_out9 = 9,
856        DSI10Dsi_out10 = 10,
857        DSI11Dsi_out11 = 11,
858        DSI12Dsi_out12 = 12,
859        DSI13Dsi_out13 = 13,
860        DSI14Dsi_out14 = 14,
861        DSI15Dsi_out15 = 15,
862        ILOInternalLowSpeedOscillator = 16,
863        WCOWatchCrystalOscillator = 17,
864        ALTLFAlternateLowFrequencyClock = 18,
865        PILOPrecisionInternalLowSpeedOscillator = 19
866    ]
867],
868CLK_PATH_SELECT0 [
869    PATH_MUX OFFSET(0) NUMBITS(3) [
870        IMOInternalRCOscillator = 0,
871        EXTCLKExternalClockPin = 1,
872        ECOExternalCrystalOscillator = 2,
873        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
874        DSI_MUX = 4
875    ]
876],
877CLK_PATH_SELECT1 [
878    PATH_MUX OFFSET(0) NUMBITS(3) [
879        IMOInternalRCOscillator = 0,
880        EXTCLKExternalClockPin = 1,
881        ECOExternalCrystalOscillator = 2,
882        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
883        DSI_MUX = 4
884    ]
885],
886CLK_PATH_SELECT2 [
887    PATH_MUX OFFSET(0) NUMBITS(3) [
888        IMOInternalRCOscillator = 0,
889        EXTCLKExternalClockPin = 1,
890        ECOExternalCrystalOscillator = 2,
891        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
892        DSI_MUX = 4
893    ]
894],
895CLK_PATH_SELECT3 [
896    PATH_MUX OFFSET(0) NUMBITS(3) [
897        IMOInternalRCOscillator = 0,
898        EXTCLKExternalClockPin = 1,
899        ECOExternalCrystalOscillator = 2,
900        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
901        DSI_MUX = 4
902    ]
903],
904CLK_PATH_SELECT4 [
905    PATH_MUX OFFSET(0) NUMBITS(3) [
906        IMOInternalRCOscillator = 0,
907        EXTCLKExternalClockPin = 1,
908        ECOExternalCrystalOscillator = 2,
909        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
910        DSI_MUX = 4
911    ]
912],
913CLK_PATH_SELECT5 [
914    PATH_MUX OFFSET(0) NUMBITS(3) [
915        IMOInternalRCOscillator = 0,
916        EXTCLKExternalClockPin = 1,
917        ECOExternalCrystalOscillator = 2,
918        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
919        DSI_MUX = 4
920    ]
921],
922CLK_PATH_SELECT6 [
923    PATH_MUX OFFSET(0) NUMBITS(3) [
924        IMOInternalRCOscillator = 0,
925        EXTCLKExternalClockPin = 1,
926        ECOExternalCrystalOscillator = 2,
927        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
928        DSI_MUX = 4
929    ]
930],
931CLK_PATH_SELECT7 [
932    PATH_MUX OFFSET(0) NUMBITS(3) [
933        IMOInternalRCOscillator = 0,
934        EXTCLKExternalClockPin = 1,
935        ECOExternalCrystalOscillator = 2,
936        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
937        DSI_MUX = 4
938    ]
939],
940CLK_PATH_SELECT8 [
941    PATH_MUX OFFSET(0) NUMBITS(3) [
942        IMOInternalRCOscillator = 0,
943        EXTCLKExternalClockPin = 1,
944        ECOExternalCrystalOscillator = 2,
945        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
946        DSI_MUX = 4
947    ]
948],
949CLK_PATH_SELECT9 [
950    PATH_MUX OFFSET(0) NUMBITS(3) [
951        IMOInternalRCOscillator = 0,
952        EXTCLKExternalClockPin = 1,
953        ECOExternalCrystalOscillator = 2,
954        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
955        DSI_MUX = 4
956    ]
957],
958CLK_PATH_SELECT10 [
959    PATH_MUX OFFSET(0) NUMBITS(3) [
960        IMOInternalRCOscillator = 0,
961        EXTCLKExternalClockPin = 1,
962        ECOExternalCrystalOscillator = 2,
963        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
964        DSI_MUX = 4
965    ]
966],
967CLK_PATH_SELECT11 [
968    PATH_MUX OFFSET(0) NUMBITS(3) [
969        IMOInternalRCOscillator = 0,
970        EXTCLKExternalClockPin = 1,
971        ECOExternalCrystalOscillator = 2,
972        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
973        DSI_MUX = 4
974    ]
975],
976CLK_PATH_SELECT12 [
977    PATH_MUX OFFSET(0) NUMBITS(3) [
978        IMOInternalRCOscillator = 0,
979        EXTCLKExternalClockPin = 1,
980        ECOExternalCrystalOscillator = 2,
981        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
982        DSI_MUX = 4
983    ]
984],
985CLK_PATH_SELECT13 [
986    PATH_MUX OFFSET(0) NUMBITS(3) [
987        IMOInternalRCOscillator = 0,
988        EXTCLKExternalClockPin = 1,
989        ECOExternalCrystalOscillator = 2,
990        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
991        DSI_MUX = 4
992    ]
993],
994CLK_PATH_SELECT14 [
995    PATH_MUX OFFSET(0) NUMBITS(3) [
996        IMOInternalRCOscillator = 0,
997        EXTCLKExternalClockPin = 1,
998        ECOExternalCrystalOscillator = 2,
999        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
1000        DSI_MUX = 4
1001    ]
1002],
1003CLK_PATH_SELECT15 [
1004    PATH_MUX OFFSET(0) NUMBITS(3) [
1005        IMOInternalRCOscillator = 0,
1006        EXTCLKExternalClockPin = 1,
1007        ECOExternalCrystalOscillator = 2,
1008        ALTHFAlternateHighFrequencyClockInputProductSpecificClock = 3,
1009        DSI_MUX = 4
1010    ]
1011],
1012CLK_ROOT_SELECT0 [
1013    ROOT_MUX OFFSET(0) NUMBITS(4) [
1014        SelectPATH0CanBeConfiguredForFLL = 0,
1015        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1016        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1017        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1018        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1019        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1020        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1021        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1022        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1023        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1024        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1025        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1026        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1027        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1028        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1029        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1030    ],
1031    ROOT_DIV OFFSET(4) NUMBITS(2) [
1032        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1033        DivideSelectedClockSourceBy2 = 1,
1034        DivideSelectedClockSourceBy4 = 2,
1035        DivideSelectedClockSourceBy8 = 3
1036    ],
1037    ENABLE OFFSET(31) NUMBITS(1) []
1038],
1039CLK_ROOT_SELECT1 [
1040    ROOT_MUX OFFSET(0) NUMBITS(4) [
1041        SelectPATH0CanBeConfiguredForFLL = 0,
1042        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1043        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1044        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1045        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1046        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1047        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1048        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1049        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1050        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1051        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1052        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1053        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1054        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1055        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1056        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1057    ],
1058    ROOT_DIV OFFSET(4) NUMBITS(2) [
1059        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1060        DivideSelectedClockSourceBy2 = 1,
1061        DivideSelectedClockSourceBy4 = 2,
1062        DivideSelectedClockSourceBy8 = 3
1063    ],
1064    ENABLE OFFSET(31) NUMBITS(1) []
1065],
1066CLK_ROOT_SELECT2 [
1067    ROOT_MUX OFFSET(0) NUMBITS(4) [
1068        SelectPATH0CanBeConfiguredForFLL = 0,
1069        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1070        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1071        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1072        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1073        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1074        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1075        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1076        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1077        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1078        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1079        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1080        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1081        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1082        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1083        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1084    ],
1085    ROOT_DIV OFFSET(4) NUMBITS(2) [
1086        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1087        DivideSelectedClockSourceBy2 = 1,
1088        DivideSelectedClockSourceBy4 = 2,
1089        DivideSelectedClockSourceBy8 = 3
1090    ],
1091    ENABLE OFFSET(31) NUMBITS(1) []
1092],
1093CLK_ROOT_SELECT3 [
1094    ROOT_MUX OFFSET(0) NUMBITS(4) [
1095        SelectPATH0CanBeConfiguredForFLL = 0,
1096        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1097        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1098        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1099        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1100        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1101        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1102        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1103        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1104        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1105        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1106        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1107        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1108        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1109        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1110        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1111    ],
1112    ROOT_DIV OFFSET(4) NUMBITS(2) [
1113        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1114        DivideSelectedClockSourceBy2 = 1,
1115        DivideSelectedClockSourceBy4 = 2,
1116        DivideSelectedClockSourceBy8 = 3
1117    ],
1118    ENABLE OFFSET(31) NUMBITS(1) []
1119],
1120CLK_ROOT_SELECT4 [
1121    ROOT_MUX OFFSET(0) NUMBITS(4) [
1122        SelectPATH0CanBeConfiguredForFLL = 0,
1123        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1124        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1125        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1126        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1127        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1128        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1129        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1130        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1131        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1132        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1133        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1134        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1135        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1136        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1137        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1138    ],
1139    ROOT_DIV OFFSET(4) NUMBITS(2) [
1140        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1141        DivideSelectedClockSourceBy2 = 1,
1142        DivideSelectedClockSourceBy4 = 2,
1143        DivideSelectedClockSourceBy8 = 3
1144    ],
1145    ENABLE OFFSET(31) NUMBITS(1) []
1146],
1147CLK_ROOT_SELECT5 [
1148    ROOT_MUX OFFSET(0) NUMBITS(4) [
1149        SelectPATH0CanBeConfiguredForFLL = 0,
1150        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1151        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1152        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1153        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1154        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1155        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1156        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1157        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1158        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1159        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1160        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1161        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1162        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1163        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1164        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1165    ],
1166    ROOT_DIV OFFSET(4) NUMBITS(2) [
1167        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1168        DivideSelectedClockSourceBy2 = 1,
1169        DivideSelectedClockSourceBy4 = 2,
1170        DivideSelectedClockSourceBy8 = 3
1171    ],
1172    ENABLE OFFSET(31) NUMBITS(1) []
1173],
1174CLK_ROOT_SELECT6 [
1175    ROOT_MUX OFFSET(0) NUMBITS(4) [
1176        SelectPATH0CanBeConfiguredForFLL = 0,
1177        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1178        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1179        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1180        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1181        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1182        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1183        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1184        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1185        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1186        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1187        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1188        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1189        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1190        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1191        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1192    ],
1193    ROOT_DIV OFFSET(4) NUMBITS(2) [
1194        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1195        DivideSelectedClockSourceBy2 = 1,
1196        DivideSelectedClockSourceBy4 = 2,
1197        DivideSelectedClockSourceBy8 = 3
1198    ],
1199    ENABLE OFFSET(31) NUMBITS(1) []
1200],
1201CLK_ROOT_SELECT7 [
1202    ROOT_MUX OFFSET(0) NUMBITS(4) [
1203        SelectPATH0CanBeConfiguredForFLL = 0,
1204        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1205        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1206        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1207        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1208        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1209        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1210        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1211        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1212        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1213        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1214        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1215        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1216        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1217        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1218        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1219    ],
1220    ROOT_DIV OFFSET(4) NUMBITS(2) [
1221        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1222        DivideSelectedClockSourceBy2 = 1,
1223        DivideSelectedClockSourceBy4 = 2,
1224        DivideSelectedClockSourceBy8 = 3
1225    ],
1226    ENABLE OFFSET(31) NUMBITS(1) []
1227],
1228CLK_ROOT_SELECT8 [
1229    ROOT_MUX OFFSET(0) NUMBITS(4) [
1230        SelectPATH0CanBeConfiguredForFLL = 0,
1231        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1232        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1233        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1234        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1235        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1236        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1237        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1238        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1239        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1240        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1241        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1242        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1243        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1244        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1245        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1246    ],
1247    ROOT_DIV OFFSET(4) NUMBITS(2) [
1248        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1249        DivideSelectedClockSourceBy2 = 1,
1250        DivideSelectedClockSourceBy4 = 2,
1251        DivideSelectedClockSourceBy8 = 3
1252    ],
1253    ENABLE OFFSET(31) NUMBITS(1) []
1254],
1255CLK_ROOT_SELECT9 [
1256    ROOT_MUX OFFSET(0) NUMBITS(4) [
1257        SelectPATH0CanBeConfiguredForFLL = 0,
1258        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1259        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1260        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1261        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1262        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1263        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1264        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1265        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1266        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1267        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1268        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1269        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1270        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1271        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1272        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1273    ],
1274    ROOT_DIV OFFSET(4) NUMBITS(2) [
1275        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1276        DivideSelectedClockSourceBy2 = 1,
1277        DivideSelectedClockSourceBy4 = 2,
1278        DivideSelectedClockSourceBy8 = 3
1279    ],
1280    ENABLE OFFSET(31) NUMBITS(1) []
1281],
1282CLK_ROOT_SELECT10 [
1283    ROOT_MUX OFFSET(0) NUMBITS(4) [
1284        SelectPATH0CanBeConfiguredForFLL = 0,
1285        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1286        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1287        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1288        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1289        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1290        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1291        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1292        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1293        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1294        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1295        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1296        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1297        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1298        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1299        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1300    ],
1301    ROOT_DIV OFFSET(4) NUMBITS(2) [
1302        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1303        DivideSelectedClockSourceBy2 = 1,
1304        DivideSelectedClockSourceBy4 = 2,
1305        DivideSelectedClockSourceBy8 = 3
1306    ],
1307    ENABLE OFFSET(31) NUMBITS(1) []
1308],
1309CLK_ROOT_SELECT11 [
1310    ROOT_MUX OFFSET(0) NUMBITS(4) [
1311        SelectPATH0CanBeConfiguredForFLL = 0,
1312        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1313        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1314        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1315        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1316        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1317        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1318        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1319        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1320        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1321        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1322        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1323        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1324        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1325        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1326        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1327    ],
1328    ROOT_DIV OFFSET(4) NUMBITS(2) [
1329        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1330        DivideSelectedClockSourceBy2 = 1,
1331        DivideSelectedClockSourceBy4 = 2,
1332        DivideSelectedClockSourceBy8 = 3
1333    ],
1334    ENABLE OFFSET(31) NUMBITS(1) []
1335],
1336CLK_ROOT_SELECT12 [
1337    ROOT_MUX OFFSET(0) NUMBITS(4) [
1338        SelectPATH0CanBeConfiguredForFLL = 0,
1339        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1340        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1341        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1342        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1343        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1344        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1345        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1346        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1347        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1348        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1349        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1350        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1351        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1352        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1353        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1354    ],
1355    ROOT_DIV OFFSET(4) NUMBITS(2) [
1356        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1357        DivideSelectedClockSourceBy2 = 1,
1358        DivideSelectedClockSourceBy4 = 2,
1359        DivideSelectedClockSourceBy8 = 3
1360    ],
1361    ENABLE OFFSET(31) NUMBITS(1) []
1362],
1363CLK_ROOT_SELECT13 [
1364    ROOT_MUX OFFSET(0) NUMBITS(4) [
1365        SelectPATH0CanBeConfiguredForFLL = 0,
1366        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1367        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1368        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1369        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1370        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1371        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1372        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1373        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1374        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1375        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1376        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1377        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1378        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1379        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1380        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1381    ],
1382    ROOT_DIV OFFSET(4) NUMBITS(2) [
1383        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1384        DivideSelectedClockSourceBy2 = 1,
1385        DivideSelectedClockSourceBy4 = 2,
1386        DivideSelectedClockSourceBy8 = 3
1387    ],
1388    ENABLE OFFSET(31) NUMBITS(1) []
1389],
1390CLK_ROOT_SELECT14 [
1391    ROOT_MUX OFFSET(0) NUMBITS(4) [
1392        SelectPATH0CanBeConfiguredForFLL = 0,
1393        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1394        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1395        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1396        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1397        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1398        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1399        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1400        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1401        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1402        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1403        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1404        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1405        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1406        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1407        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1408    ],
1409    ROOT_DIV OFFSET(4) NUMBITS(2) [
1410        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1411        DivideSelectedClockSourceBy2 = 1,
1412        DivideSelectedClockSourceBy4 = 2,
1413        DivideSelectedClockSourceBy8 = 3
1414    ],
1415    ENABLE OFFSET(31) NUMBITS(1) []
1416],
1417CLK_ROOT_SELECT15 [
1418    ROOT_MUX OFFSET(0) NUMBITS(4) [
1419        SelectPATH0CanBeConfiguredForFLL = 0,
1420        SelectPATH1CanBeConfiguredForPLL0IfAvailableInTheProduct = 1,
1421        SelectPATH2CanBeConfiguredForPLL1IfAvailableInTheProduct = 2,
1422        SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct = 3,
1423        SelectPATH4CanBeConfiguredForPLL3IfAvailableInTheProduct = 4,
1424        SelectPATH5CanBeConfiguredForPLL4IfAvailableInTheProduct = 5,
1425        SelectPATH6CanBeConfiguredForPLL5IfAvailableInTheProduct = 6,
1426        SelectPATH7CanBeConfiguredForPLL6IfAvailableInTheProduct = 7,
1427        SelectPATH8CanBeConfiguredForPLL7IfAvailableInTheProduct = 8,
1428        SelectPATH9CanBeConfiguredForPLL8IfAvailableInTheProduct = 9,
1429        SelectPATH10CanBeConfiguredForPLL9IfAvailableInTheProduct = 10,
1430        SelectPATH11CanBeConfiguredForPLL10IfAvailableInTheProduct = 11,
1431        SelectPATH12CanBeConfiguredForPLL11IfAvailableInTheProduct = 12,
1432        SelectPATH13CanBeConfiguredForPLL12IfAvailableInTheProduct = 13,
1433        SelectPATH14CanBeConfiguredForPLL13IfAvailableInTheProduct = 14,
1434        SelectPATH15CanBeConfiguredForPLL14IfAvailableInTheProduct = 15
1435    ],
1436    ROOT_DIV OFFSET(4) NUMBITS(2) [
1437        TransparentModeFeedThroughSelectedClockSourceWODividing = 0,
1438        DivideSelectedClockSourceBy2 = 1,
1439        DivideSelectedClockSourceBy4 = 2,
1440        DivideSelectedClockSourceBy8 = 3
1441    ],
1442    ENABLE OFFSET(31) NUMBITS(1) []
1443],
1444CLK_PLL_CONFIG0 [
1445    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1446    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1447    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1448    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1449    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1450        AUTO = 0,
1451        SameAsAUTO = 1,
1452        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1453        SelectPLLOutputIgnoresLockIndicator = 3
1454    ],
1455    ENABLE OFFSET(31) NUMBITS(1) []
1456],
1457CLK_PLL_CONFIG1 [
1458    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1459    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1460    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1461    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1462    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1463        AUTO = 0,
1464        SameAsAUTO = 1,
1465        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1466        SelectPLLOutputIgnoresLockIndicator = 3
1467    ],
1468    ENABLE OFFSET(31) NUMBITS(1) []
1469],
1470CLK_PLL_CONFIG2 [
1471    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1472    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1473    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1474    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1475    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1476        AUTO = 0,
1477        SameAsAUTO = 1,
1478        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1479        SelectPLLOutputIgnoresLockIndicator = 3
1480    ],
1481    ENABLE OFFSET(31) NUMBITS(1) []
1482],
1483CLK_PLL_CONFIG3 [
1484    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1485    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1486    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1487    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1488    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1489        AUTO = 0,
1490        SameAsAUTO = 1,
1491        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1492        SelectPLLOutputIgnoresLockIndicator = 3
1493    ],
1494    ENABLE OFFSET(31) NUMBITS(1) []
1495],
1496CLK_PLL_CONFIG4 [
1497    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1498    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1499    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1500    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1501    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1502        AUTO = 0,
1503        SameAsAUTO = 1,
1504        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1505        SelectPLLOutputIgnoresLockIndicator = 3
1506    ],
1507    ENABLE OFFSET(31) NUMBITS(1) []
1508],
1509CLK_PLL_CONFIG5 [
1510    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1511    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1512    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1513    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1514    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1515        AUTO = 0,
1516        SameAsAUTO = 1,
1517        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1518        SelectPLLOutputIgnoresLockIndicator = 3
1519    ],
1520    ENABLE OFFSET(31) NUMBITS(1) []
1521],
1522CLK_PLL_CONFIG6 [
1523    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1524    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1525    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1526    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1527    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1528        AUTO = 0,
1529        SameAsAUTO = 1,
1530        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1531        SelectPLLOutputIgnoresLockIndicator = 3
1532    ],
1533    ENABLE OFFSET(31) NUMBITS(1) []
1534],
1535CLK_PLL_CONFIG7 [
1536    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1537    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1538    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1539    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1540    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1541        AUTO = 0,
1542        SameAsAUTO = 1,
1543        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1544        SelectPLLOutputIgnoresLockIndicator = 3
1545    ],
1546    ENABLE OFFSET(31) NUMBITS(1) []
1547],
1548CLK_PLL_CONFIG8 [
1549    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1550    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1551    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1552    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1553    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1554        AUTO = 0,
1555        SameAsAUTO = 1,
1556        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1557        SelectPLLOutputIgnoresLockIndicator = 3
1558    ],
1559    ENABLE OFFSET(31) NUMBITS(1) []
1560],
1561CLK_PLL_CONFIG9 [
1562    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1563    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1564    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1565    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1566    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1567        AUTO = 0,
1568        SameAsAUTO = 1,
1569        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1570        SelectPLLOutputIgnoresLockIndicator = 3
1571    ],
1572    ENABLE OFFSET(31) NUMBITS(1) []
1573],
1574CLK_PLL_CONFIG10 [
1575    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1576    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1577    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1578    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1579    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1580        AUTO = 0,
1581        SameAsAUTO = 1,
1582        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1583        SelectPLLOutputIgnoresLockIndicator = 3
1584    ],
1585    ENABLE OFFSET(31) NUMBITS(1) []
1586],
1587CLK_PLL_CONFIG11 [
1588    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1589    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1590    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1591    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1592    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1593        AUTO = 0,
1594        SameAsAUTO = 1,
1595        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1596        SelectPLLOutputIgnoresLockIndicator = 3
1597    ],
1598    ENABLE OFFSET(31) NUMBITS(1) []
1599],
1600CLK_PLL_CONFIG12 [
1601    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1602    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1603    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1604    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1605    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1606        AUTO = 0,
1607        SameAsAUTO = 1,
1608        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1609        SelectPLLOutputIgnoresLockIndicator = 3
1610    ],
1611    ENABLE OFFSET(31) NUMBITS(1) []
1612],
1613CLK_PLL_CONFIG13 [
1614    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1615    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1616    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1617    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1618    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1619        AUTO = 0,
1620        SameAsAUTO = 1,
1621        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1622        SelectPLLOutputIgnoresLockIndicator = 3
1623    ],
1624    ENABLE OFFSET(31) NUMBITS(1) []
1625],
1626CLK_PLL_CONFIG14 [
1627    FEEDBACK_DIV OFFSET(0) NUMBITS(7) [],
1628    REFERENCE_DIV OFFSET(8) NUMBITS(5) [],
1629    OUTPUT_DIV OFFSET(16) NUMBITS(5) [],
1630    PLL_LF_MODE OFFSET(27) NUMBITS(1) [],
1631    BYPASS_SEL OFFSET(28) NUMBITS(2) [
1632        AUTO = 0,
1633        SameAsAUTO = 1,
1634        SelectPLLReferenceInputBypassModeIgnoresLockIndicator = 2,
1635        SelectPLLOutputIgnoresLockIndicator = 3
1636    ],
1637    ENABLE OFFSET(31) NUMBITS(1) []
1638],
1639CLK_PLL_STATUS0 [
1640    LOCKED OFFSET(0) NUMBITS(1) [],
1641    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1642],
1643CLK_PLL_STATUS1 [
1644    LOCKED OFFSET(0) NUMBITS(1) [],
1645    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1646],
1647CLK_PLL_STATUS2 [
1648    LOCKED OFFSET(0) NUMBITS(1) [],
1649    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1650],
1651CLK_PLL_STATUS3 [
1652    LOCKED OFFSET(0) NUMBITS(1) [],
1653    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1654],
1655CLK_PLL_STATUS4 [
1656    LOCKED OFFSET(0) NUMBITS(1) [],
1657    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1658],
1659CLK_PLL_STATUS5 [
1660    LOCKED OFFSET(0) NUMBITS(1) [],
1661    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1662],
1663CLK_PLL_STATUS6 [
1664    LOCKED OFFSET(0) NUMBITS(1) [],
1665    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1666],
1667CLK_PLL_STATUS7 [
1668    LOCKED OFFSET(0) NUMBITS(1) [],
1669    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1670],
1671CLK_PLL_STATUS8 [
1672    LOCKED OFFSET(0) NUMBITS(1) [],
1673    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1674],
1675CLK_PLL_STATUS9 [
1676    LOCKED OFFSET(0) NUMBITS(1) [],
1677    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1678],
1679CLK_PLL_STATUS10 [
1680    LOCKED OFFSET(0) NUMBITS(1) [],
1681    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1682],
1683CLK_PLL_STATUS11 [
1684    LOCKED OFFSET(0) NUMBITS(1) [],
1685    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1686],
1687CLK_PLL_STATUS12 [
1688    LOCKED OFFSET(0) NUMBITS(1) [],
1689    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1690],
1691CLK_PLL_STATUS13 [
1692    LOCKED OFFSET(0) NUMBITS(1) [],
1693    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1694],
1695CLK_PLL_STATUS14 [
1696    LOCKED OFFSET(0) NUMBITS(1) [],
1697    UNLOCK_OCCURRED OFFSET(1) NUMBITS(1) []
1698]
1699];
1700const SRSS_BASE: StaticRef<SrssRegisters> =
1701    unsafe { StaticRef::new(0x40260000 as *const SrssRegisters) };
1702
1703pub struct Srss {
1704    registers: StaticRef<SrssRegisters>,
1705}
1706
1707impl Srss {
1708    pub const fn new() -> Srss {
1709        Srss {
1710            registers: SRSS_BASE,
1711        }
1712    }
1713
1714    pub fn init_clock(&self) {
1715        self.registers
1716            .clk_path_select_3
1717            .modify(CLK_PATH_SELECT3::PATH_MUX::IMOInternalRCOscillator);
1718
1719        self.registers.clk_root_select_0.modify(CLK_ROOT_SELECT0::ENABLE::SET + CLK_ROOT_SELECT0::ROOT_MUX::SelectPATH3CanBeConfiguredForPLL2IfAvailableInTheProduct + CLK_ROOT_SELECT0::ROOT_DIV::TransparentModeFeedThroughSelectedClockSourceWODividing);
1720    }
1721}
psoc62xa/srss.rs

psoc62xa/
srss.rs
