psoc62xa/
cpuss.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright OxidOS Automotive 2025 SRL.
4
5use kernel::utilities::registers::{
6    interfaces::ReadWriteable, register_bitfields, register_structs, ReadOnly, ReadWrite,
7};
8use kernel::utilities::StaticRef;
9
10register_structs! {
11    CpussRegisters {
12        (0x000 => identity: ReadOnly<u32, IDENTITY::Register>),
13        (0x004 => cm4_status: ReadOnly<u32, CM4_STATUS::Register>),
14        (0x008 => cm4_clock_ctl: ReadWrite<u32>),
15        (0x00C => cm4_ctl: ReadWrite<u32, CM4_CTL::Register>),
16        (0x010 => _reserved0),
17        (0x200 => cm4_vector_table_base: ReadWrite<u32>),
18        (0x204 => _reserved1),
19        (0x240 => cm4_nmi_ctl_0: ReadWrite<u32>),
20        (0x244 => cm4_nmi_ctl_1: ReadWrite<u32>),
21        (0x248 => cm4_nmi_ctl_2: ReadWrite<u32>),
22        (0x24C => cm4_nmi_ctl_3: ReadWrite<u32>),
23        (0x250 => _reserved2),
24        (0x1000 => cm0_ctl: ReadWrite<u32, CM0_CTL::Register>),
25        (0x1004 => cm0_status: ReadOnly<u32, CM0_STATUS::Register>),
26        (0x1008 => cm0_clock_ctl: ReadWrite<u32, CM0_CLOCK_CTL::Register>),
27        (0x100C => _reserved3),
28        (0x1100 => cm0_int0_status: ReadOnly<u32, CM0_INT0_STATUS::Register>),
29        (0x1104 => cm0_int1_status: ReadOnly<u32, CM0_INT1_STATUS::Register>),
30        (0x1108 => cm0_int2_status: ReadOnly<u32, CM0_INT2_STATUS::Register>),
31        (0x110C => cm0_int3_status: ReadOnly<u32, CM0_INT3_STATUS::Register>),
32        (0x1110 => cm0_int4_status: ReadOnly<u32, CM0_INT4_STATUS::Register>),
33        (0x1114 => cm0_int5_status: ReadOnly<u32, CM0_INT5_STATUS::Register>),
34        (0x1118 => cm0_int6_status: ReadOnly<u32, CM0_INT6_STATUS::Register>),
35        (0x111C => cm0_int7_status: ReadOnly<u32, CM0_INT7_STATUS::Register>),
36        (0x1120 => cm0_vector_table_base: ReadWrite<u32>),
37        (0x1124 => _reserved4),
38        (0x1140 => cm0_nmi_ctl_0: ReadWrite<u32>),
39        (0x1144 => cm0_nmi_ctl_1: ReadWrite<u32>),
40        (0x1148 => cm0_nmi_ctl_2: ReadWrite<u32>),
41        (0x114C => cm0_nmi_ctl_3: ReadWrite<u32>),
42        (0x1150 => _reserved5),
43        (0x1200 => cm4_pwr_ctl: ReadWrite<u32, CM4_PWR_CTL::Register>),
44        (0x1204 => cm4_pwr_delay_ctl: ReadWrite<u32>),
45        (0x1208 => _reserved6),
46        (0x1300 => ram0_ctl0: ReadWrite<u32, RAM0_CTL0::Register>),
47        (0x1304 => ram0_status: ReadOnly<u32>),
48        (0x1308 => _reserved7),
49        (0x1340 => ram0_pwr_macro_ctl_0: ReadWrite<u32, RAM0_PWR_MACRO_CTL0::Register>),
50        (0x1344 => ram0_pwr_macro_ctl_1: ReadWrite<u32, RAM0_PWR_MACRO_CTL1::Register>),
51        (0x1348 => ram0_pwr_macro_ctl_2: ReadWrite<u32, RAM0_PWR_MACRO_CTL2::Register>),
52        (0x134C => ram0_pwr_macro_ctl_3: ReadWrite<u32, RAM0_PWR_MACRO_CTL3::Register>),
53        (0x1350 => ram0_pwr_macro_ctl_4: ReadWrite<u32, RAM0_PWR_MACRO_CTL4::Register>),
54        (0x1354 => ram0_pwr_macro_ctl_5: ReadWrite<u32, RAM0_PWR_MACRO_CTL5::Register>),
55        (0x1358 => ram0_pwr_macro_ctl_6: ReadWrite<u32, RAM0_PWR_MACRO_CTL6::Register>),
56        (0x135C => ram0_pwr_macro_ctl_7: ReadWrite<u32, RAM0_PWR_MACRO_CTL7::Register>),
57        (0x1360 => ram0_pwr_macro_ctl_8: ReadWrite<u32, RAM0_PWR_MACRO_CTL8::Register>),
58        (0x1364 => ram0_pwr_macro_ctl_9: ReadWrite<u32, RAM0_PWR_MACRO_CTL9::Register>),
59        (0x1368 => ram0_pwr_macro_ctl_10: ReadWrite<u32, RAM0_PWR_MACRO_CTL10::Register>),
60        (0x136C => ram0_pwr_macro_ctl_11: ReadWrite<u32, RAM0_PWR_MACRO_CTL11::Register>),
61        (0x1370 => ram0_pwr_macro_ctl_12: ReadWrite<u32, RAM0_PWR_MACRO_CTL12::Register>),
62        (0x1374 => ram0_pwr_macro_ctl_13: ReadWrite<u32, RAM0_PWR_MACRO_CTL13::Register>),
63        (0x1378 => ram0_pwr_macro_ctl_14: ReadWrite<u32, RAM0_PWR_MACRO_CTL14::Register>),
64        (0x137C => ram0_pwr_macro_ctl_15: ReadWrite<u32, RAM0_PWR_MACRO_CTL15::Register>),
65        (0x1380 => ram1_ctl0: ReadWrite<u32, RAM1_CTL0::Register>),
66        (0x1384 => ram1_status: ReadOnly<u32>),
67        (0x1388 => ram1_pwr_ctl: ReadWrite<u32, RAM1_PWR_CTL::Register>),
68        (0x138C => _reserved8),
69        (0x13A0 => ram2_ctl0: ReadWrite<u32, RAM2_CTL0::Register>),
70        (0x13A4 => ram2_status: ReadOnly<u32>),
71        (0x13A8 => ram2_pwr_ctl: ReadWrite<u32, RAM2_PWR_CTL::Register>),
72        (0x13AC => _reserved9),
73        (0x13C0 => ram_pwr_delay_ctl: ReadWrite<u32>),
74        (0x13C4 => rom_ctl: ReadWrite<u32, ROM_CTL::Register>),
75        (0x13C8 => ecc_ctl: ReadWrite<u32, ECC_CTL::Register>),
76        (0x13CC => _reserved10),
77        (0x1400 => product_id: ReadOnly<u32, PRODUCT_ID::Register>),
78        (0x1404 => _reserved11),
79        (0x1410 => dp_status: ReadOnly<u32, DP_STATUS::Register>),
80        (0x1414 => ap_ctl: ReadWrite<u32, AP_CTL::Register>),
81        (0x1418 => _reserved12),
82        (0x1500 => buff_ctl: ReadWrite<u32>),
83        (0x1504 => _reserved13),
84        (0x1600 => systick_ctl: ReadWrite<u32, SYSTICK_CTL::Register>),
85        (0x1604 => _reserved14),
86        (0x1704 => mbist_stat: ReadOnly<u32, MBIST_STAT::Register>),
87        (0x1708 => _reserved15),
88        (0x1800 => cal_sup_set: ReadWrite<u32>),
89        (0x1804 => cal_sup_clr: ReadWrite<u32>),
90        (0x1808 => _reserved16),
91        (0x2000 => cm0_pc_ctl: ReadWrite<u32>),
92        (0x2004 => _reserved17),
93        (0x2040 => cm0_pc0_handler: ReadWrite<u32>),
94        (0x2044 => cm0_pc1_handler: ReadWrite<u32>),
95        (0x2048 => cm0_pc2_handler: ReadWrite<u32>),
96        (0x204C => cm0_pc3_handler: ReadWrite<u32>),
97        (0x2050 => _reserved18),
98        (0x20C4 => protection: ReadWrite<u32>),
99        (0x20C8 => _reserved19),
100        (0x2100 => trim_rom_ctl: ReadWrite<u32>),
101        (0x2104 => trim_ram_ctl: ReadWrite<u32>),
102        (0x2108 => _reserved20),
103        (0x8000 => cm0_system_int_ctl: [ReadWrite<u32, CM0_SYSTEM_INT_CTL::Register>; 168]),
104        (0x82A0 => @END),
105    }
106}
107register_bitfields![u32,
108IDENTITY [
109    P OFFSET(0) NUMBITS(1) [],
110    NS OFFSET(1) NUMBITS(1) [],
111    PC OFFSET(4) NUMBITS(4) [],
112    MS OFFSET(8) NUMBITS(4) []
113],
114CM4_STATUS [
115    SLEEPING OFFSET(0) NUMBITS(1) [],
116    SLEEPDEEP OFFSET(1) NUMBITS(1) [],
117    PWR_DONE OFFSET(4) NUMBITS(1) []
118],
119CM4_CLOCK_CTL [
120    FAST_INT_DIV OFFSET(8) NUMBITS(8) []
121],
122CM4_CTL [
123    IOC_MASK OFFSET(24) NUMBITS(1) [],
124    DZC_MASK OFFSET(25) NUMBITS(1) [],
125    OFC_MASK OFFSET(26) NUMBITS(1) [],
126    UFC_MASK OFFSET(27) NUMBITS(1) [],
127    IXC_MASK OFFSET(28) NUMBITS(1) [],
128    IDC_MASK OFFSET(31) NUMBITS(1) []
129],
130CM4_INT0_STATUS [
131    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
132    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
133],
134CM4_INT1_STATUS [
135    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
136    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
137],
138CM4_INT2_STATUS [
139    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
140    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
141],
142CM4_INT3_STATUS [
143    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
144    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
145],
146CM4_INT4_STATUS [
147    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
148    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
149],
150CM4_INT5_STATUS [
151    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
152    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
153],
154CM4_INT6_STATUS [
155    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
156    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
157],
158CM4_INT7_STATUS [
159    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
160    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
161],
162CM4_VECTOR_TABLE_BASE [
163    ADDR22 OFFSET(10) NUMBITS(22) []
164],
165UDB_PWR_CTL [
166    PWR_MODE OFFSET(0) NUMBITS(2) [
167        SeeCM4_PWR_CTL = 0
168    ],
169    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
170],
171UDB_PWR_DELAY_CTL [
172    UP OFFSET(0) NUMBITS(10) []
173],
174CM0_CTL [
175    SLV_STALL OFFSET(0) NUMBITS(1) [],
176    ENABLED OFFSET(1) NUMBITS(1) [],
177    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
178],
179CM0_STATUS [
180    SLEEPING OFFSET(0) NUMBITS(1) [],
181    SLEEPDEEP OFFSET(1) NUMBITS(1) []
182],
183CM0_CLOCK_CTL [
184    SLOW_INT_DIV OFFSET(8) NUMBITS(8) [],
185    PERI_INT_DIV OFFSET(24) NUMBITS(8) []
186],
187CM0_INT0_STATUS [
188    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
189    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
190],
191CM0_INT1_STATUS [
192    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
193    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
194],
195CM0_INT2_STATUS [
196    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
197    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
198],
199CM0_INT3_STATUS [
200    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
201    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
202],
203CM0_INT4_STATUS [
204    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
205    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
206],
207CM0_INT5_STATUS [
208    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
209    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
210],
211CM0_INT6_STATUS [
212    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
213    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
214],
215CM0_INT7_STATUS [
216    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) [],
217    SYSTEM_INT_VALID OFFSET(31) NUMBITS(1) []
218],
219CM0_VECTOR_TABLE_BASE [
220    ADDR24 OFFSET(8) NUMBITS(24) []
221],
222CM4_PWR_CTL [
223    PWR_MODE OFFSET(0) NUMBITS(2) [
224        SwitchCM4OffPowerOffClockOffIsolateResetAndNoRetain = 0,
225        RESET = 1,
226        RETAINED = 2,
227        SwitchCM4OnPowerOnClockOnNoIsolateNoResetAndNoRetain = 3
228    ],
229    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
230],
231CM4_PWR_DELAY_CTL [
232    UP OFFSET(0) NUMBITS(10) []
233],
234RAM0_CTL0 [
235    SLOW_WS OFFSET(0) NUMBITS(2) [],
236    FAST_WS OFFSET(8) NUMBITS(2) [],
237    ECC_EN OFFSET(16) NUMBITS(1) [],
238    ECC_AUTO_CORRECT OFFSET(17) NUMBITS(1) [],
239    ECC_INJ_EN OFFSET(18) NUMBITS(1) []
240],
241RAM0_STATUS [
242    WB_EMPTY OFFSET(0) NUMBITS(1) []
243],
244RAM1_CTL0 [
245    SLOW_WS OFFSET(0) NUMBITS(2) [],
246    FAST_WS OFFSET(8) NUMBITS(2) [],
247    ECC_EN OFFSET(16) NUMBITS(1) [],
248    ECC_AUTO_CORRECT OFFSET(17) NUMBITS(1) [],
249    ECC_INJ_EN OFFSET(18) NUMBITS(1) []
250],
251RAM1_STATUS [
252    WB_EMPTY OFFSET(0) NUMBITS(1) []
253],
254RAM1_PWR_CTL [
255    PWR_MODE OFFSET(0) NUMBITS(2) [
256        SeeRAM0_PWR_MACRO_CTL = 0,
257        Undefined = 1
258    ],
259    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
260],
261RAM2_CTL0 [
262    SLOW_WS OFFSET(0) NUMBITS(2) [],
263    FAST_WS OFFSET(8) NUMBITS(2) [],
264    ECC_EN OFFSET(16) NUMBITS(1) [],
265    ECC_AUTO_CORRECT OFFSET(17) NUMBITS(1) [],
266    ECC_INJ_EN OFFSET(18) NUMBITS(1) []
267],
268RAM2_STATUS [
269    WB_EMPTY OFFSET(0) NUMBITS(1) []
270],
271RAM2_PWR_CTL [
272    PWR_MODE OFFSET(0) NUMBITS(2) [
273        SeeRAM0_PWR_MACRO_CTL = 0,
274        Undefined = 1
275    ],
276    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
277],
278RAM_PWR_DELAY_CTL [
279    UP OFFSET(0) NUMBITS(10) []
280],
281ROM_CTL [
282    SLOW_WS OFFSET(0) NUMBITS(2) [],
283    FAST_WS OFFSET(8) NUMBITS(2) []
284],
285ECC_CTL [
286    WORD_ADDR OFFSET(0) NUMBITS(25) [],
287    PARITY OFFSET(25) NUMBITS(7) []
288],
289PRODUCT_ID [
290    FAMILY_ID OFFSET(0) NUMBITS(12) [],
291    MAJOR_REV OFFSET(16) NUMBITS(4) [],
292    MINOR_REV OFFSET(20) NUMBITS(4) []
293],
294DP_STATUS [
295    SWJ_CONNECTED OFFSET(0) NUMBITS(1) [],
296    SWJ_DEBUG_EN OFFSET(1) NUMBITS(1) [],
297    SWJ_JTAG_SEL OFFSET(2) NUMBITS(1) []
298],
299AP_CTL [
300    CM0_ENABLE OFFSET(0) NUMBITS(1) [],
301    CM4_ENABLE OFFSET(1) NUMBITS(1) [],
302    SYS_ENABLE OFFSET(2) NUMBITS(1) [],
303    CM0_DISABLE OFFSET(16) NUMBITS(1) [],
304    CM4_DISABLE OFFSET(17) NUMBITS(1) [],
305    SYS_DISABLE OFFSET(18) NUMBITS(1) []
306],
307BUFF_CTL [
308    WRITE_BUFF OFFSET(0) NUMBITS(1) []
309],
310SYSTICK_CTL [
311    TENMS OFFSET(0) NUMBITS(24) [],
312    CLOCK_SOURCE OFFSET(24) NUMBITS(2) [],
313    SKEW OFFSET(30) NUMBITS(1) [],
314    NOREF OFFSET(31) NUMBITS(1) []
315],
316MBIST_STAT [
317    SFP_READY OFFSET(0) NUMBITS(1) [],
318    SFP_FAIL OFFSET(1) NUMBITS(1) []
319],
320CAL_SUP_SET [
321    DATA OFFSET(0) NUMBITS(32) []
322],
323CAL_SUP_CLR [
324    DATA OFFSET(0) NUMBITS(32) []
325],
326CM0_PC_CTL [
327    VALID OFFSET(0) NUMBITS(4) []
328],
329CM0_PC0_HANDLER [
330    ADDR OFFSET(0) NUMBITS(32) []
331],
332CM0_PC1_HANDLER [
333    ADDR OFFSET(0) NUMBITS(32) []
334],
335CM0_PC2_HANDLER [
336    ADDR OFFSET(0) NUMBITS(32) []
337],
338CM0_PC3_HANDLER [
339    ADDR OFFSET(0) NUMBITS(32) []
340],
341PROTECTION [
342    STATE OFFSET(0) NUMBITS(3) []
343],
344TRIM_ROM_CTL [
345    TRIM OFFSET(0) NUMBITS(32) []
346],
347TRIM_RAM_CTL [
348    TRIM OFFSET(0) NUMBITS(32) []
349],
350CM4_NMI_CTL0 [
351    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) []
352],
353CM4_NMI_CTL1 [
354    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) []
355],
356CM4_NMI_CTL2 [
357    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) []
358],
359CM4_NMI_CTL3 [
360    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) []
361],
362CM0_NMI_CTL0 [
363    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) []
364],
365CM0_NMI_CTL1 [
366    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) []
367],
368CM0_NMI_CTL2 [
369    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) []
370],
371CM0_NMI_CTL3 [
372    SYSTEM_INT_IDX OFFSET(0) NUMBITS(10) []
373],
374RAM0_PWR_MACRO_CTL0 [
375    PWR_MODE OFFSET(0) NUMBITS(2) [
376        OFF = 0,
377        Undefined = 1,
378        RETAINED = 2,
379        ENABLED = 3
380    ],
381    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
382],
383RAM0_PWR_MACRO_CTL1 [
384    PWR_MODE OFFSET(0) NUMBITS(2) [
385        OFF = 0,
386        Undefined = 1,
387        RETAINED = 2,
388        ENABLED = 3
389    ],
390    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
391],
392RAM0_PWR_MACRO_CTL2 [
393    PWR_MODE OFFSET(0) NUMBITS(2) [
394        OFF = 0,
395        Undefined = 1,
396        RETAINED = 2,
397        ENABLED = 3
398    ],
399    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
400],
401RAM0_PWR_MACRO_CTL3 [
402    PWR_MODE OFFSET(0) NUMBITS(2) [
403        OFF = 0,
404        Undefined = 1,
405        RETAINED = 2,
406        ENABLED = 3
407    ],
408    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
409],
410RAM0_PWR_MACRO_CTL4 [
411    PWR_MODE OFFSET(0) NUMBITS(2) [
412        OFF = 0,
413        Undefined = 1,
414        RETAINED = 2,
415        ENABLED = 3
416    ],
417    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
418],
419RAM0_PWR_MACRO_CTL5 [
420    PWR_MODE OFFSET(0) NUMBITS(2) [
421        OFF = 0,
422        Undefined = 1,
423        RETAINED = 2,
424        ENABLED = 3
425    ],
426    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
427],
428RAM0_PWR_MACRO_CTL6 [
429    PWR_MODE OFFSET(0) NUMBITS(2) [
430        OFF = 0,
431        Undefined = 1,
432        RETAINED = 2,
433        ENABLED = 3
434    ],
435    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
436],
437RAM0_PWR_MACRO_CTL7 [
438    PWR_MODE OFFSET(0) NUMBITS(2) [
439        OFF = 0,
440        Undefined = 1,
441        RETAINED = 2,
442        ENABLED = 3
443    ],
444    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
445],
446RAM0_PWR_MACRO_CTL8 [
447    PWR_MODE OFFSET(0) NUMBITS(2) [
448        OFF = 0,
449        Undefined = 1,
450        RETAINED = 2,
451        ENABLED = 3
452    ],
453    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
454],
455RAM0_PWR_MACRO_CTL9 [
456    PWR_MODE OFFSET(0) NUMBITS(2) [
457        OFF = 0,
458        Undefined = 1,
459        RETAINED = 2,
460        ENABLED = 3
461    ],
462    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
463],
464RAM0_PWR_MACRO_CTL10 [
465    PWR_MODE OFFSET(0) NUMBITS(2) [
466        OFF = 0,
467        Undefined = 1,
468        RETAINED = 2,
469        ENABLED = 3
470    ],
471    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
472],
473RAM0_PWR_MACRO_CTL11 [
474    PWR_MODE OFFSET(0) NUMBITS(2) [
475        OFF = 0,
476        Undefined = 1,
477        RETAINED = 2,
478        ENABLED = 3
479    ],
480    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
481],
482RAM0_PWR_MACRO_CTL12 [
483    PWR_MODE OFFSET(0) NUMBITS(2) [
484        OFF = 0,
485        Undefined = 1,
486        RETAINED = 2,
487        ENABLED = 3
488    ],
489    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
490],
491RAM0_PWR_MACRO_CTL13 [
492    PWR_MODE OFFSET(0) NUMBITS(2) [
493        OFF = 0,
494        Undefined = 1,
495        RETAINED = 2,
496        ENABLED = 3
497    ],
498    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
499],
500RAM0_PWR_MACRO_CTL14 [
501    PWR_MODE OFFSET(0) NUMBITS(2) [
502        OFF = 0,
503        Undefined = 1,
504        RETAINED = 2,
505        ENABLED = 3
506    ],
507    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
508],
509RAM0_PWR_MACRO_CTL15 [
510    PWR_MODE OFFSET(0) NUMBITS(2) [
511        OFF = 0,
512        Undefined = 1,
513        RETAINED = 2,
514        ENABLED = 3
515    ],
516    VECTKEYSTAT OFFSET(16) NUMBITS(16) []
517],
518CM0_SYSTEM_INT_CTL [
519    CPU_INT_IDX OFFSET(0) NUMBITS(3) [],
520    CPU_INT_VALID OFFSET(31) NUMBITS(1) []
521],
522];
523const CPUSS_BASE: StaticRef<CpussRegisters> =
524    unsafe { StaticRef::new(0x40200000 as *const CpussRegisters) };
525
526const SCB5_ID: usize = 44;
527const TCPWM0_ID: usize = 123;
528
529pub struct Cpuss {
530    registers: StaticRef<CpussRegisters>,
531}
532
533impl Cpuss {
534    pub const fn new() -> Cpuss {
535        Cpuss {
536            registers: CPUSS_BASE,
537        }
538    }
539
540    pub fn init_clock(&self) {
541        self.registers
542            .cm0_clock_ctl
543            .modify(CM0_CLOCK_CTL::PERI_INT_DIV.val(0));
544    }
545
546    pub fn enable_int_for_scb5(&self) {
547        self.registers.cm0_system_int_ctl[SCB5_ID].modify(
548            CM0_SYSTEM_INT_CTL::CPU_INT_IDX.val(0) + CM0_SYSTEM_INT_CTL::CPU_INT_VALID::SET,
549        );
550    }
551
552    pub fn enable_int_for_tcpwm00(&self) {
553        self.registers.cm0_system_int_ctl[TCPWM0_ID].modify(
554            CM0_SYSTEM_INT_CTL::CPU_INT_IDX.val(0) + CM0_SYSTEM_INT_CTL::CPU_INT_VALID::SET,
555        );
556    }
557
558    pub fn enable_int_for_gpio0(&self) {
559        self.registers.cm0_system_int_ctl[15].modify(
560            CM0_SYSTEM_INT_CTL::CPU_INT_IDX.val(1) + CM0_SYSTEM_INT_CTL::CPU_INT_VALID::SET,
561        );
562    }
563}
psoc62xa/cpuss.rs

psoc62xa/
cpuss.rs
