lpc55s6x/
lib.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2025.
4
5#![no_std]
6// IOCON has many register definitions in `register_structs()!`
7// and requires a deeper recursion limit than the default to fully expand.
8#![recursion_limit = "512"]
9
10use cortexm33::{initialize_ram_jump_to_main, unhandled_interrupt, CortexM33, CortexMVariant};
11
12pub mod chip;
13pub mod clocks;
14pub mod ctimer0;
15pub mod flexcomm;
16pub mod gpio;
17pub mod inputmux;
18pub mod interrupts;
19pub mod iocon;
20pub mod pint;
21pub mod uart;
22
23extern "C" {
24    fn _estack();
25}
26
27#[cfg_attr(
28    all(target_arch = "arm", target_os = "none"),
29    link_section = ".vectors"
30)]
31#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
32pub static BASE_VECTORS: [unsafe extern "C" fn(); 16] = [
33    _estack,
34    initialize_ram_jump_to_main,
35    unhandled_interrupt,
36    CortexM33::HARD_FAULT_HANDLER,
37    unhandled_interrupt,
38    unhandled_interrupt,
39    unhandled_interrupt,
40    unhandled_interrupt,
41    unhandled_interrupt,
42    unhandled_interrupt,
43    unhandled_interrupt,
44    CortexM33::SVC_HANDLER,
45    unhandled_interrupt,
46    unhandled_interrupt,
47    unhandled_interrupt,
48    CortexM33::SYSTICK_HANDLER,
49];
50
51#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")]
52#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
53pub static IRQS: [unsafe extern "C" fn(); 60] = [
54    CortexM33::GENERIC_ISR,
55    CortexM33::GENERIC_ISR,
56    CortexM33::GENERIC_ISR,
57    CortexM33::GENERIC_ISR,
58    CortexM33::GENERIC_ISR,
59    CortexM33::GENERIC_ISR,
60    CortexM33::GENERIC_ISR,
61    CortexM33::GENERIC_ISR,
62    CortexM33::GENERIC_ISR,
63    CortexM33::GENERIC_ISR,
64    CortexM33::GENERIC_ISR,
65    CortexM33::GENERIC_ISR,
66    CortexM33::GENERIC_ISR,
67    CortexM33::GENERIC_ISR,
68    CortexM33::GENERIC_ISR,
69    CortexM33::GENERIC_ISR,
70    CortexM33::GENERIC_ISR,
71    CortexM33::GENERIC_ISR,
72    CortexM33::GENERIC_ISR,
73    CortexM33::GENERIC_ISR,
74    CortexM33::GENERIC_ISR,
75    CortexM33::GENERIC_ISR,
76    CortexM33::GENERIC_ISR,
77    CortexM33::GENERIC_ISR,
78    CortexM33::GENERIC_ISR,
79    CortexM33::GENERIC_ISR,
80    CortexM33::GENERIC_ISR,
81    CortexM33::GENERIC_ISR,
82    CortexM33::GENERIC_ISR,
83    CortexM33::GENERIC_ISR,
84    CortexM33::GENERIC_ISR,
85    CortexM33::GENERIC_ISR,
86    CortexM33::GENERIC_ISR,
87    CortexM33::GENERIC_ISR,
88    CortexM33::GENERIC_ISR,
89    CortexM33::GENERIC_ISR,
90    CortexM33::GENERIC_ISR,
91    CortexM33::GENERIC_ISR,
92    CortexM33::GENERIC_ISR,
93    CortexM33::GENERIC_ISR,
94    CortexM33::GENERIC_ISR,
95    CortexM33::GENERIC_ISR,
96    CortexM33::GENERIC_ISR,
97    CortexM33::GENERIC_ISR,
98    CortexM33::GENERIC_ISR,
99    CortexM33::GENERIC_ISR,
100    CortexM33::GENERIC_ISR,
101    CortexM33::GENERIC_ISR,
102    CortexM33::GENERIC_ISR,
103    CortexM33::GENERIC_ISR,
104    CortexM33::GENERIC_ISR,
105    CortexM33::GENERIC_ISR,
106    CortexM33::GENERIC_ISR,
107    CortexM33::GENERIC_ISR,
108    CortexM33::GENERIC_ISR,
109    CortexM33::GENERIC_ISR,
110    CortexM33::GENERIC_ISR,
111    CortexM33::GENERIC_ISR,
112    CortexM33::GENERIC_ISR,
113    CortexM33::GENERIC_ISR,
114];
115
116pub unsafe fn init() {
117    cortexm33::nvic::disable_all();
118    cortexm33::nvic::clear_all_pending();
119
120    // Set the vector table offset, which requires casting from a BASE_VECTORS to a *const ()
121    // pointer.
122    let vector_table: *const [unsafe extern "C" fn(); 16] = core::ptr::addr_of!(BASE_VECTORS);
123    let vector_table: *const () = vector_table.cast();
124    cortexm33::scb::set_vector_table_offset(vector_table);
125
126    cortexm33::nvic::enable_all();
127}
lpc55s6x/lib.rs

lpc55s6x/
lib.rs
