lpc55s6x/clocks/syscon.rs
1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2025.
4
5//! System Controller (SYSCON) register definitions for the LPC55S6x family.
6//!
7//! The SYSCON block provides global system configuration and control,
8//! including:
9//! - Memory remap and AHB matrix priorities
10//! - Peripheral reset and clock gating (AHBCLKCTRLx, PRESETCTRLx)
11//! - Clock source selection and dividers for timers, Flexcomm, ADC, USB, etc.
12//! - PLL configuration and status
13//! - CPU control, debug features, and device identification
14//!
15//! Reference: *LPC55S6x/LPC55S2x/LPC552x User Manual* (NXP).
16
17use kernel::utilities::registers::{
18 register_bitfields, register_structs, ReadOnly, ReadWrite, WriteOnly,
19};
20use kernel::utilities::StaticRef;
21
22register_structs! {
23 /// SYSCON
24 pub SysconRegisters {
25 /// Memory Remap control register
26 (0x000 => memoryremap: ReadWrite<u32, MEMORYREMAP::Register>),
27 (0x004 => _reserved0),
28 /// AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest
29 (0x010 => ahbmatprio: ReadWrite<u32, AHBMATPRIO::Register>),
30 (0x014 => _reserved1),
31 /// System tick calibration for secure part of CPU0
32 (0x038 => cpu0stckcal: ReadWrite<u32, CPU0STCKCAL::Register>),
33 /// System tick calibration for non-secure part of CPU0
34 (0x03C => cpu0nstckcal: ReadWrite<u32, CPU0NSTCKCAL::Register>),
35 /// System tick calibration for CPU1
36 (0x040 => cpu1stckcal: ReadWrite<u32, CPU1STCKCAL::Register>),
37 (0x044 => _reserved2),
38 /// NMI Source Select
39 (0x048 => nmisrc: ReadWrite<u32, NMISRC::Register>),
40 (0x04C => _reserved3),
41 /// Peripheral reset control 0
42 (0x100 => pub presetctrl0: ReadWrite<u32, PRESETCTRL0::Register>),
43 /// Peripheral reset control 1
44 (0x104 => presetctrl1: ReadWrite<u32, PRESETCTRL1::Register>),
45 /// Peripheral reset control 2
46 (0x108 => presetctrl2: ReadWrite<u32, PRESETCTRL2::Register>),
47 (0x10C => _reserved4),
48 /// Peripheral reset control set register
49 (0x120 => presetctrlset_0: ReadWrite<u32, PRESETCTRLSET0::Register>),
50 /// Peripheral reset control set register
51 (0x124 => presetctrlset_1: ReadWrite<u32, PRESETCTRLSET1::Register>),
52 /// Peripheral reset control set register
53 (0x128 => presetctrlset_2: ReadWrite<u32, PRESETCTRLSET2::Register>),
54 (0x12C => _reserved5),
55 /// Peripheral reset control clear register
56 (0x140 => presetctrlclr_0: ReadWrite<u32>),
57 /// Peripheral reset control clear register
58 (0x144 => presetctrlclr_1: ReadWrite<u32>),
59 /// Peripheral reset control clear register
60 (0x148 => presetctrlclr_2: ReadWrite<u32>),
61 (0x14C => _reserved6),
62 /// generate a software_reset
63 (0x160 => swr_reset: WriteOnly<u32>),
64 (0x164 => _reserved7),
65 /// AHB Clock control 0
66 (0x200 => pub ahbclkctrl0: ReadWrite<u32, AHBCLKCTRL0::Register>),
67 /// AHB Clock control 1
68 (0x204 => pub ahbclkctrl1: ReadWrite<u32, AHBCLKCTRL1::Register>),
69 /// AHB Clock control 2
70 (0x208 => ahbclkctrl2: ReadWrite<u32, AHBCLKCTRL2::Register>),
71 (0x20C => _reserved8),
72 /// Peripheral reset control register
73 (0x220 => pub ahbclkctrlset_0: ReadWrite<u32, AHBCLKCTRLSET0::Register>),
74 /// Peripheral reset control register
75 (0x224 => ahbclkctrlset_1: ReadWrite<u32, AHBCLKCTRLSET1::Register>),
76 /// Peripheral reset control register
77 (0x228 => ahbclkctrlset_2: ReadWrite<u32, AHBCLKCTRLSET2::Register>),
78 (0x22C => _reserved9),
79 /// Peripheral reset control register
80 (0x240 => ahbclkctrlclr_0: ReadWrite<u32, AHBCLKCTRLCLR0::Register>),
81 /// Peripheral reset control register
82 (0x244 => ahbclkctrlclr_1: ReadWrite<u32, AHBCLKCTRLCLR1::Register>),
83 /// Peripheral reset control register
84 (0x248 => ahbclkctrlclr_2: ReadWrite<u32, AHBCLKCTRLCLR2::Register>),
85 (0x24C => _reserved10),
86 /// System Tick Timer for CPU0 source select
87 (0x260 => systickclksel0: ReadWrite<u32>),
88 /// System Tick Timer for CPU1 source select
89 (0x264 => systickclksel1: ReadWrite<u32>),
90 /// Trace clock source select
91 (0x268 => traceclksel: ReadWrite<u32>),
92 /// CTimer 0 clock source select
93 (0x26C => pub ctimerclksel0: ReadWrite<u32, CTIMERCLKSEL0::Register>),
94 /// CTimer 1 clock source select
95 (0x270 => ctimerclksel1: ReadWrite<u32>),
96 /// CTimer 2 clock source select
97 (0x274 => ctimerclksel2: ReadWrite<u32>),
98 /// CTimer 3 clock source select
99 (0x278 => ctimerclksel3: ReadWrite<u32>),
100 /// CTimer 4 clock source select
101 (0x27C => ctimerclksel4: ReadWrite<u32>),
102 /// Main clock A source select
103 (0x280 => mainclksela: ReadWrite<u32>),
104 /// Main clock source select
105 (0x284 => mainclkselb: ReadWrite<u32>),
106 /// CLKOUT clock source select
107 (0x288 => pub clkoutsel: ReadWrite<u32, CLKOUTSEL::Register>),
108 (0x28C => _reserved11),
109 /// PLL0 clock source select
110 (0x290 => pll0clksel: ReadWrite<u32>),
111 /// PLL1 clock source select
112 (0x294 => pll1clksel: ReadWrite<u32>),
113 (0x298 => _reserved12),
114 /// ADC clock source select
115 (0x2A4 => adcclksel: ReadWrite<u32>),
116 /// FS USB clock source select
117 (0x2A8 => usb0clksel: ReadWrite<u32>),
118 (0x2AC => _reserved13),
119 /// Flexcomm Interface 0 clock source select for Fractional Rate Divider
120 (0x2B0 => pub fcclksel0: ReadWrite<u32, FCCLKSEL::Register>),
121 /// Flexcomm Interface 1 clock source select for Fractional Rate Divider
122 (0x2B4 => pub fcclksel1: ReadWrite<u32, FCCLKSEL::Register>),
123 /// Flexcomm Interface 2 clock source select for Fractional Rate Divider
124 (0x2B8 => pub fcclksel2: ReadWrite<u32, FCCLKSEL::Register>),
125 /// Flexcomm Interface 3 clock source select for Fractional Rate Divider
126 (0x2BC => pub fcclksel3: ReadWrite<u32, FCCLKSEL::Register>),
127 /// Flexcomm Interface 4 clock source select for Fractional Rate Divider
128 (0x2C0 => pub fcclksel4: ReadWrite<u32, FCCLKSEL::Register>),
129 /// Flexcomm Interface 5 clock source select for Fractional Rate Divider
130 (0x2C4 => pub fcclksel5: ReadWrite<u32, FCCLKSEL::Register>),
131 /// Flexcomm Interface 6 clock source select for Fractional Rate Divider
132 (0x2C8 => pub fcclksel6: ReadWrite<u32, FCCLKSEL::Register>),
133 /// Flexcomm Interface 7 clock source select for Fractional Rate Divider
134 (0x2CC => pub fcclksel7: ReadWrite<u32, FCCLKSEL::Register>),
135 /// HS LSPI clock source select
136 (0x2D0 => hslspiclksel: ReadWrite<u32>),
137 (0x2D4 => _reserved14),
138 /// MCLK clock source select
139 (0x2E0 => mclkclksel: ReadWrite<u32>),
140 (0x2E4 => _reserved15),
141 /// SCTimer/PWM clock source select
142 (0x2F0 => sctclksel: ReadWrite<u32>),
143 (0x2F4 => _reserved16),
144 /// SDIO clock source select
145 (0x2F8 => sdioclksel: ReadWrite<u32>),
146 (0x2FC => _reserved17),
147 /// System Tick Timer divider for CPU0
148 (0x300 => systickclkdiv0: ReadWrite<u32, SYSTICKCLKDIV0::Register>),
149 /// System Tick Timer divider for CPU1
150 (0x304 => systickclkdiv1: ReadWrite<u32, SYSTICKCLKDIV1::Register>),
151 /// TRACE clock divider
152 (0x308 => traceclkdiv: ReadWrite<u32, TRACECLKDIV::Register>),
153 (0x30C => _reserved18),
154 /// Fractional rate divider for flexcomm 0
155 (0x320 => flexfrg0ctrl: ReadWrite<u32, FLEXFRG0CTRL::Register>),
156 /// Fractional rate divider for flexcomm 1
157 (0x324 => flexfrg1ctrl: ReadWrite<u32, FLEXFRG1CTRL::Register>),
158 /// Fractional rate divider for flexcomm 2
159 (0x328 => flexfrg2ctrl: ReadWrite<u32, FLEXFRG2CTRL::Register>),
160 /// Fractional rate divider for flexcomm 3
161 (0x32C => flexfrg3ctrl: ReadWrite<u32, FLEXFRG3CTRL::Register>),
162 /// Fractional rate divider for flexcomm 4
163 (0x330 => flexfrg4ctrl: ReadWrite<u32, FLEXFRG4CTRL::Register>),
164 /// Fractional rate divider for flexcomm 5
165 (0x334 => flexfrg5ctrl: ReadWrite<u32, FLEXFRG5CTRL::Register>),
166 /// Fractional rate divider for flexcomm 6
167 (0x338 => flexfrg6ctrl: ReadWrite<u32, FLEXFRG6CTRL::Register>),
168 /// Fractional rate divider for flexcomm 7
169 (0x33C => flexfrg7ctrl: ReadWrite<u32, FLEXFRG7CTRL::Register>),
170 (0x340 => _reserved19),
171 /// System clock divider
172 (0x380 => ahbclkdiv: ReadWrite<u32, AHBCLKDIV::Register>),
173 /// CLKOUT clock divider
174 (0x384 => clkoutdiv: ReadWrite<u32, CLKOUTDIV::Register>),
175 /// FRO_HF (96MHz) clock divider
176 (0x388 => frohfdiv: ReadWrite<u32, FROHFDIV::Register>),
177 /// WDT clock divider
178 (0x38C => wdtclkdiv: ReadWrite<u32, WDTCLKDIV::Register>),
179 (0x390 => _reserved20),
180 /// ADC clock divider
181 (0x394 => adcclkdiv: ReadWrite<u32, ADCCLKDIV::Register>),
182 /// USB0 Clock divider
183 (0x398 => usb0clkdiv: ReadWrite<u32, USB0CLKDIV::Register>),
184 (0x39C => _reserved21),
185 /// I2S MCLK clock divider
186 (0x3AC => mclkdiv: ReadWrite<u32, MCLKDIV::Register>),
187 (0x3B0 => _reserved22),
188 /// SCT/PWM clock divider
189 (0x3B4 => sctclkdiv: ReadWrite<u32, SCTCLKDIV::Register>),
190 (0x3B8 => _reserved23),
191 /// SDIO clock divider
192 (0x3BC => sdioclkdiv: ReadWrite<u32, SDIOCLKDIV::Register>),
193 (0x3C0 => _reserved24),
194 /// PLL0 clock divider
195 (0x3C4 => pll0clkdiv: ReadWrite<u32, PLL0CLKDIV::Register>),
196 (0x3C8 => _reserved25),
197 /// Control clock configuration registers access (like xxxDIV, xxxSEL)
198 (0x3FC => clockgenupdatelockout: ReadWrite<u32>),
199 /// FMC configuration register
200 (0x400 => fmccr: ReadWrite<u32, FMCCR::Register>),
201 (0x404 => _reserved26),
202 /// USB0 need clock control
203 (0x40C => usb0needclkctrl: ReadWrite<u32, USB0NEEDCLKCTRL::Register>),
204 /// USB0 need clock status
205 (0x410 => usb0needclkstat: ReadWrite<u32, USB0NEEDCLKSTAT::Register>),
206 (0x414 => _reserved27),
207 /// FMCflush control
208 (0x41C => fmcflush: WriteOnly<u32>),
209 /// MCLK control
210 (0x420 => mclkio: ReadWrite<u32>),
211 /// USB1 need clock control
212 (0x424 => usb1needclkctrl: ReadWrite<u32, USB1NEEDCLKCTRL::Register>),
213 /// USB1 need clock status
214 (0x428 => usb1needclkstat: ReadWrite<u32, USB1NEEDCLKSTAT::Register>),
215 (0x42C => _reserved28),
216 /// SDIO CCLKIN phase and delay control
217 (0x460 => sdioclkctrl: ReadWrite<u32, SDIOCLKCTRL::Register>),
218 (0x464 => _reserved29),
219 /// PLL1 550m control
220 (0x560 => pll1ctrl: ReadWrite<u32, PLL1CTRL::Register>),
221 /// PLL1 550m status
222 (0x564 => pll1stat: ReadWrite<u32, PLL1STAT::Register>),
223 /// PLL1 550m N divider
224 (0x568 => pll1ndec: ReadWrite<u32, PLL1NDEC::Register>),
225 /// PLL1 550m M divider
226 (0x56C => pll1mdec: ReadWrite<u32, PLL1MDEC::Register>),
227 /// PLL1 550m P divider
228 (0x570 => pll1pdec: ReadWrite<u32, PLL1PDEC::Register>),
229 (0x574 => _reserved30),
230 /// PLL0 550m control
231 (0x580 => pll0ctrl: ReadWrite<u32, PLL0CTRL::Register>),
232 /// PLL0 550m status
233 (0x584 => pll0stat: ReadWrite<u32, PLL0STAT::Register>),
234 /// PLL0 550m N divider
235 (0x588 => pll0ndec: ReadWrite<u32, PLL0NDEC::Register>),
236 /// PLL0 550m P divider
237 (0x58C => pll0pdec: ReadWrite<u32, PLL0PDEC::Register>),
238 /// PLL0 Spread Spectrum Wrapper control register 0
239 (0x590 => pll0sscg0: ReadWrite<u32>),
240 /// PLL0 Spread Spectrum Wrapper control register 1
241 (0x594 => pll0sscg1: ReadWrite<u32, PLL0SSCG1::Register>),
242 (0x598 => _reserved31),
243 /// Functional retention control register
244 (0x704 => funcretentionctrl: ReadWrite<u32, FUNCRETENTIONCTRL::Register>),
245 (0x708 => _reserved32),
246 /// CPU Control for multiple processors
247 (0x800 => cpuctrl: ReadWrite<u32, CPUCTRL::Register>),
248 /// Coprocessor Boot Address
249 (0x804 => cpboot: ReadWrite<u32>),
250 (0x808 => _reserved33),
251 /// CPU Status
252 (0x80C => cpstat: ReadWrite<u32, CPSTAT::Register>),
253 (0x810 => _reserved34),
254 /// Various system clock controls : Flash clock (48 MHz) control, clocks to Frequenc
255 (0xA18 => clock_ctrl: ReadWrite<u32, CLOCK_CTRL::Register>),
256 (0xA1C => _reserved35),
257 /// Comparator Interrupt control
258 (0xB10 => comp_int_ctrl: ReadWrite<u32, COMP_INT_CTRL::Register>),
259 /// Comparator Interrupt status
260 (0xB14 => comp_int_status: ReadWrite<u32, COMP_INT_STATUS::Register>),
261 (0xB18 => _reserved36),
262 /// Control automatic clock gating
263 (0xE04 => autoclkgateoverride: ReadWrite<u32, AUTOCLKGATEOVERRIDE::Register>),
264 /// Enable bypass of the first stage of synchonization inside GPIO_INT module
265 (0xE08 => gpiopsync: ReadWrite<u32>),
266 (0xE0C => _reserved37),
267 /// Control write access to security registers.
268 (0xFA0 => debug_lock_en: ReadWrite<u32>),
269 /// Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control.
270 (0xFA4 => debug_features: ReadWrite<u32, DEBUG_FEATURES::Register>),
271 /// Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE r
272 (0xFA8 => debug_features_dp: ReadWrite<u32, DEBUG_FEATURES_DP::Register>),
273 (0xFAC => _reserved38),
274 /// block quiddikey/PUF all index.
275 (0xFBC => key_block: WriteOnly<u32>),
276 /// Debug authentication BEACON register
277 (0xFC0 => debug_auth_beacon: ReadWrite<u32>),
278 (0xFC4 => _reserved39),
279 /// CPUs configuration register
280 (0xFD4 => cpucfg: ReadWrite<u32>),
281 (0xFD8 => _reserved40),
282 /// Device ID
283 (0xFF8 => device_id0: ReadOnly<u32>),
284 /// Chip revision ID and Number
285 (0xFFC => dieid: ReadOnly<u32, DIEID::Register>),
286 (0x1000 => @END),
287 }
288}
289register_bitfields![u32,
290MEMORYREMAP [
291 /// Select the location of the vector table :.
292 MAP OFFSET(0) NUMBITS(2) [
293 /// Vector Table in ROM.
294 VectorTableInROM = 0,
295 /// Vector Table in RAM.
296 VectorTableInRAM = 1,
297 /// Vector Table in Flash.
298 VectorTableInFlash = 2
299 ]
300],
301AHBMATPRIO [
302 /// CPU0 C-AHB bus.
303 PRI_CPU0_CBUS OFFSET(0) NUMBITS(2) [],
304 /// CPU0 S-AHB bus.
305 PRI_CPU0_SBUS OFFSET(2) NUMBITS(2) [],
306 /// CPU1 C-AHB bus.
307 PRI_CPU1_CBUS OFFSET(4) NUMBITS(2) [],
308 /// CPU1 S-AHB bus.
309 PRI_CPU1_SBUS OFFSET(6) NUMBITS(2) [],
310 /// USB-FS.(USB0)
311 PRI_USB_FS OFFSET(8) NUMBITS(2) [],
312 /// DMA0 controller priority.
313 PRI_SDMA0 OFFSET(10) NUMBITS(2) [],
314 /// SDIO.
315 PRI_SDIO OFFSET(16) NUMBITS(2) [],
316 /// PQ (HW Accelerator).
317 PRI_PQ OFFSET(18) NUMBITS(2) [],
318 /// HASH_AES.
319 PRI_HASH_AES OFFSET(20) NUMBITS(2) [],
320 /// USB-HS.(USB1)
321 PRI_USB_HS OFFSET(22) NUMBITS(2) [],
322 /// DMA1 controller priority.
323 PRI_SDMA1 OFFSET(24) NUMBITS(2) []
324],
325CPU0STCKCAL [
326 /// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If th
327 TENMS OFFSET(0) NUMBITS(24) [],
328 /// Initial value for the Systick timer.
329 SKEW OFFSET(24) NUMBITS(1) [],
330 /// Indicates whether the device provides a reference clock to the processor: 0 = re
331 NOREF OFFSET(25) NUMBITS(1) []
332],
333CPU0NSTCKCAL [
334 /// Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If
335 TENMS OFFSET(0) NUMBITS(24) [],
336 /// Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS
337 SKEW OFFSET(24) NUMBITS(1) [],
338 /// Initial value for the Systick timer.
339 NOREF OFFSET(25) NUMBITS(1) []
340],
341CPU1STCKCAL [
342 /// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If th
343 TENMS OFFSET(0) NUMBITS(24) [],
344 /// Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS
345 SKEW OFFSET(24) NUMBITS(1) [],
346 /// Indicates whether the device provides a reference clock to the processor: 0 = re
347 NOREF OFFSET(25) NUMBITS(1) []
348],
349NMISRC [
350 /// The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) fo
351 IRQCPU0 OFFSET(0) NUMBITS(6) [],
352 /// The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) fo
353 IRQCPU1 OFFSET(8) NUMBITS(6) [],
354 /// Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected
355 NMIENCPU1 OFFSET(30) NUMBITS(1) [],
356 /// Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected
357 NMIENCPU0 OFFSET(31) NUMBITS(1) []
358],
359PRESETCTRL0 [
360 /// ROM reset control.
361 ROM_RST OFFSET(1) NUMBITS(1) [
362 /// Bloc is not reset.
363 BlocIsNotReset = 0,
364 /// Bloc is reset.
365 BlocIsReset = 1
366 ],
367 /// SRAM Controller 1 reset control.
368 SRAM_CTRL1_RST OFFSET(3) NUMBITS(1) [
369 /// Bloc is not reset.
370 BlocIsNotReset = 0,
371 /// Bloc is reset.
372 BlocIsReset = 1
373 ],
374 /// SRAM Controller 2 reset control.
375 SRAM_CTRL2_RST OFFSET(4) NUMBITS(1) [
376 /// Bloc is not reset.
377 BlocIsNotReset = 0,
378 /// Bloc is reset.
379 BlocIsReset = 1
380 ],
381 /// SRAM Controller 3 reset control.
382 SRAM_CTRL3_RST OFFSET(5) NUMBITS(1) [
383 /// Bloc is not reset.
384 BlocIsNotReset = 0,
385 /// Bloc is reset.
386 BlocIsReset = 1
387 ],
388 /// SRAM Controller 4 reset control.
389 SRAM_CTRL4_RST OFFSET(6) NUMBITS(1) [
390 /// Bloc is not reset.
391 BlocIsNotReset = 0,
392 /// Bloc is reset.
393 BlocIsReset = 1
394 ],
395 /// Flash controller reset control.
396 FLASH_RST OFFSET(7) NUMBITS(1) [
397 /// Bloc is not reset.
398 BlocIsNotReset = 0,
399 /// Bloc is reset.
400 BlocIsReset = 1
401 ],
402 /// FMC controller reset control.
403 FMC_RST OFFSET(8) NUMBITS(1) [
404 /// Bloc is not reset.
405 BlocIsNotReset = 0,
406 /// Bloc is reset.
407 BlocIsReset = 1
408 ],
409 /// Input Mux reset control.
410 MUX_RST OFFSET(11) NUMBITS(1) [
411 /// Bloc is not reset.
412 BlocIsNotReset = 0,
413 /// Bloc is reset.
414 BlocIsReset = 1
415 ],
416 /// I/O controller reset control.
417 IOCON_RST OFFSET(13) NUMBITS(1) [
418 /// Bloc is not reset.
419 BlocIsNotReset = 0,
420 /// Bloc is reset.
421 BlocIsReset = 1
422 ],
423 /// GPIO0 reset control.
424 GPIO0_RST OFFSET(14) NUMBITS(1) [
425 /// Bloc is not reset.
426 BlocIsNotReset = 0,
427 /// Bloc is reset.
428 BlocIsReset = 1
429 ],
430 /// GPIO1 reset control.
431 GPIO1_RST OFFSET(15) NUMBITS(1) [
432 /// Bloc is not reset.
433 BlocIsNotReset = 0,
434 /// Bloc is reset.
435 BlocIsReset = 1
436 ],
437 /// GPIO2 reset control.
438 GPIO2_RST OFFSET(16) NUMBITS(1) [
439 /// Bloc is not reset.
440 BlocIsNotReset = 0,
441 /// Bloc is reset.
442 BlocIsReset = 1
443 ],
444 /// GPIO3 reset control.
445 GPIO3_RST OFFSET(17) NUMBITS(1) [
446 /// Bloc is not reset.
447 BlocIsNotReset = 0,
448 /// Bloc is reset.
449 BlocIsReset = 1
450 ],
451 /// Pin interrupt (PINT) reset control.
452 PINT_RST OFFSET(18) NUMBITS(1) [
453 /// Bloc is not reset.
454 BlocIsNotReset = 0,
455 /// Bloc is reset.
456 BlocIsReset = 1
457 ],
458 /// Group interrupt (GINT) reset control.
459 GINT_RST OFFSET(19) NUMBITS(1) [
460 /// Bloc is not reset.
461 BlocIsNotReset = 0,
462 /// Bloc is reset.
463 BlocIsReset = 1
464 ],
465 /// DMA0 reset control.
466 DMA0_RST OFFSET(20) NUMBITS(1) [
467 /// Bloc is not reset.
468 BlocIsNotReset = 0,
469 /// Bloc is reset.
470 BlocIsReset = 1
471 ],
472 /// CRCGEN reset control.
473 CRCGEN_RST OFFSET(21) NUMBITS(1) [
474 /// Bloc is not reset.
475 BlocIsNotReset = 0,
476 /// Bloc is reset.
477 BlocIsReset = 1
478 ],
479 /// Watchdog Timer reset control.
480 WWDT_RST OFFSET(22) NUMBITS(1) [
481 /// Bloc is not reset.
482 BlocIsNotReset = 0,
483 /// Bloc is reset.
484 BlocIsReset = 1
485 ],
486 /// Real Time Clock (RTC) reset control.
487 RTC_RST OFFSET(23) NUMBITS(1) [
488 /// Bloc is not reset.
489 BlocIsNotReset = 0,
490 /// Bloc is reset.
491 BlocIsReset = 1
492 ],
493 /// Inter CPU communication Mailbox reset control.
494 MAILBOX_RST OFFSET(26) NUMBITS(1) [
495 /// Bloc is not reset.
496 BlocIsNotReset = 0,
497 /// Bloc is reset.
498 BlocIsReset = 1
499 ],
500 /// ADC reset control.
501 ADC_RST OFFSET(27) NUMBITS(1) [
502 /// Bloc is not reset.
503 BlocIsNotReset = 0,
504 /// Bloc is reset.
505 BlocIsReset = 1
506 ]
507],
508PRESETCTRLX0 [
509 /// Data array value
510 DATA OFFSET(0) NUMBITS(32) []
511],
512PRESETCTRL1 [
513 /// MRT reset control.
514 MRT_RST OFFSET(0) NUMBITS(1) [
515 /// Bloc is not reset.
516 BlocIsNotReset = 0,
517 /// Bloc is reset.
518 BlocIsReset = 1
519 ],
520 /// OS Event Timer reset control.
521 OSTIMER_RST OFFSET(1) NUMBITS(1) [
522 /// Bloc is not reset.
523 BlocIsNotReset = 0,
524 /// Bloc is reset.
525 BlocIsReset = 1
526 ],
527 /// SCT reset control.
528 SCT_RST OFFSET(2) NUMBITS(1) [
529 /// Bloc is not reset.
530 BlocIsNotReset = 0,
531 /// Bloc is reset.
532 BlocIsReset = 1
533 ],
534 /// SCTIPU reset control.
535 SCTIPU_RST OFFSET(6) NUMBITS(1) [
536 /// Bloc is not reset.
537 BlocIsNotReset = 0,
538 /// Bloc is reset.
539 BlocIsReset = 1
540 ],
541 /// UTICK reset control.
542 UTICK_RST OFFSET(10) NUMBITS(1) [
543 /// Bloc is not reset.
544 BlocIsNotReset = 0,
545 /// Bloc is reset.
546 BlocIsReset = 1
547 ],
548 /// FC0 reset control.
549 FC0_RST OFFSET(11) NUMBITS(1) [
550 /// Bloc is not reset.
551 BlocIsNotReset = 0,
552 /// Bloc is reset.
553 BlocIsReset = 1
554 ],
555 /// FC1 reset control.
556 FC1_RST OFFSET(12) NUMBITS(1) [
557 /// Bloc is not reset.
558 BlocIsNotReset = 0,
559 /// Bloc is reset.
560 BlocIsReset = 1
561 ],
562 /// FC2 reset control.
563 FC2_RST OFFSET(13) NUMBITS(1) [
564 /// Bloc is not reset.
565 BlocIsNotReset = 0,
566 /// Bloc is reset.
567 BlocIsReset = 1
568 ],
569 /// FC3 reset control.
570 FC3_RST OFFSET(14) NUMBITS(1) [
571 /// Bloc is not reset.
572 BlocIsNotReset = 0,
573 /// Bloc is reset.
574 BlocIsReset = 1
575 ],
576 /// FC4 reset control.
577 FC4_RST OFFSET(15) NUMBITS(1) [
578 /// Bloc is not reset.
579 BlocIsNotReset = 0,
580 /// Bloc is reset.
581 BlocIsReset = 1
582 ],
583 /// FC5 reset control.
584 FC5_RST OFFSET(16) NUMBITS(1) [
585 /// Bloc is not reset.
586 BlocIsNotReset = 0,
587 /// Bloc is reset.
588 BlocIsReset = 1
589 ],
590 /// FC6 reset control.
591 FC6_RST OFFSET(17) NUMBITS(1) [
592 /// Bloc is not reset.
593 BlocIsNotReset = 0,
594 /// Bloc is reset.
595 BlocIsReset = 1
596 ],
597 /// FC7 reset control.
598 FC7_RST OFFSET(18) NUMBITS(1) [
599 /// Bloc is not reset.
600 BlocIsNotReset = 0,
601 /// Bloc is reset.
602 BlocIsReset = 1
603 ],
604 /// Timer 2 reset control.
605 TIMER2_RST OFFSET(22) NUMBITS(1) [
606 /// Bloc is not reset.
607 BlocIsNotReset = 0,
608 /// Bloc is reset.
609 BlocIsReset = 1
610 ],
611 /// USB0 DEV reset control.
612 USB0_DEV_RST OFFSET(25) NUMBITS(1) [
613 /// Bloc is not reset.
614 BlocIsNotReset = 0,
615 /// Bloc is reset.
616 BlocIsReset = 1
617 ],
618 /// Timer 0 reset control.
619 TIMER0_RST OFFSET(26) NUMBITS(1) [
620 /// Bloc is not reset.
621 BlocIsNotReset = 0,
622 /// Bloc is reset.
623 BlocIsReset = 1
624 ],
625 /// Timer 1 reset control.
626 TIMER1_RST OFFSET(27) NUMBITS(1) [
627 /// Bloc is not reset.
628 BlocIsNotReset = 0,
629 /// Bloc is reset.
630 BlocIsReset = 1
631 ]
632],
633PRESETCTRLX1 [
634 /// Data array value
635 DATA OFFSET(0) NUMBITS(32) []
636],
637PRESETCTRL2 [
638 /// DMA1 reset control.
639 DMA1_RST OFFSET(1) NUMBITS(1) [
640 /// Bloc is not reset.
641 BlocIsNotReset = 0,
642 /// Bloc is reset.
643 BlocIsReset = 1
644 ],
645 /// Comparator reset control.
646 COMP_RST OFFSET(2) NUMBITS(1) [
647 /// Bloc is not reset.
648 BlocIsNotReset = 0,
649 /// Bloc is reset.
650 BlocIsReset = 1
651 ],
652 /// SDIO reset control.
653 SDIO_RST OFFSET(3) NUMBITS(1) [
654 /// Bloc is not reset.
655 BlocIsNotReset = 0,
656 /// Bloc is reset.
657 BlocIsReset = 1
658 ],
659 /// USB1 Host reset control.
660 USB1_HOST_RST OFFSET(4) NUMBITS(1) [
661 /// Bloc is not reset.
662 BlocIsNotReset = 0,
663 /// Bloc is reset.
664 BlocIsReset = 1
665 ],
666 /// USB1 dev reset control.
667 USB1_DEV_RST OFFSET(5) NUMBITS(1) [
668 /// Bloc is not reset.
669 BlocIsNotReset = 0,
670 /// Bloc is reset.
671 BlocIsReset = 1
672 ],
673 /// USB1 RAM reset control.
674 USB1_RAM_RST OFFSET(6) NUMBITS(1) [
675 /// Bloc is not reset.
676 BlocIsNotReset = 0,
677 /// Bloc is reset.
678 BlocIsReset = 1
679 ],
680 /// USB1 PHY reset control.
681 USB1_PHY_RST OFFSET(7) NUMBITS(1) [
682 /// Bloc is not reset.
683 BlocIsNotReset = 0,
684 /// Bloc is reset.
685 BlocIsReset = 1
686 ],
687 /// Frequency meter reset control.
688 FREQME_RST OFFSET(8) NUMBITS(1) [
689 /// Bloc is not reset.
690 BlocIsNotReset = 0,
691 /// Bloc is reset.
692 BlocIsReset = 1
693 ],
694 /// RNG reset control.
695 RNG_RST OFFSET(13) NUMBITS(1) [
696 /// Bloc is not reset.
697 BlocIsNotReset = 0,
698 /// Bloc is reset.
699 BlocIsReset = 1
700 ],
701 /// SYSCTL Block reset.
702 SYSCTL_RST OFFSET(15) NUMBITS(1) [
703 /// Bloc is not reset.
704 BlocIsNotReset = 0,
705 /// Bloc is reset.
706 BlocIsReset = 1
707 ],
708 /// USB0 Host Master reset control.
709 USB0_HOSTM_RST OFFSET(16) NUMBITS(1) [
710 /// Bloc is not reset.
711 BlocIsNotReset = 0,
712 /// Bloc is reset.
713 BlocIsReset = 1
714 ],
715 /// USB0 Host Slave reset control.
716 USB0_HOSTS_RST OFFSET(17) NUMBITS(1) [
717 /// Bloc is not reset.
718 BlocIsNotReset = 0,
719 /// Bloc is reset.
720 BlocIsReset = 1
721 ],
722 /// HASH_AES reset control.
723 HASH_AES_RST OFFSET(18) NUMBITS(1) [
724 /// Bloc is not reset.
725 BlocIsNotReset = 0,
726 /// Bloc is reset.
727 BlocIsReset = 1
728 ],
729 /// Power Quad reset control.
730 PQ_RST OFFSET(19) NUMBITS(1) [
731 /// Bloc is not reset.
732 BlocIsNotReset = 0,
733 /// Bloc is reset.
734 BlocIsReset = 1
735 ],
736 /// PLU LUT reset control.
737 PLULUT_RST OFFSET(20) NUMBITS(1) [
738 /// Bloc is not reset.
739 BlocIsNotReset = 0,
740 /// Bloc is reset.
741 BlocIsReset = 1
742 ],
743 /// Timer 3 reset control.
744 TIMER3_RST OFFSET(21) NUMBITS(1) [
745 /// Bloc is not reset.
746 BlocIsNotReset = 0,
747 /// Bloc is reset.
748 BlocIsReset = 1
749 ],
750 /// Timer 4 reset control.
751 TIMER4_RST OFFSET(22) NUMBITS(1) [
752 /// Bloc is not reset.
753 BlocIsNotReset = 0,
754 /// Bloc is reset.
755 BlocIsReset = 1
756 ],
757 /// PUF reset control reset control.
758 PUF_RST OFFSET(23) NUMBITS(1) [
759 /// Bloc is not reset.
760 BlocIsNotReset = 0,
761 /// Bloc is reset.
762 BlocIsReset = 1
763 ],
764 /// Casper reset control.
765 CASPER_RST OFFSET(24) NUMBITS(1) [
766 /// Bloc is not reset.
767 BlocIsNotReset = 0,
768 /// Bloc is reset.
769 BlocIsReset = 1
770 ],
771 /// analog control reset control.
772 ANALOG_CTRL_RST OFFSET(27) NUMBITS(1) [
773 /// Bloc is not reset.
774 BlocIsNotReset = 0,
775 /// Bloc is reset.
776 BlocIsReset = 1
777 ],
778 /// HS LSPI reset control.
779 HS_LSPI_RST OFFSET(28) NUMBITS(1) [
780 /// Bloc is not reset.
781 BlocIsNotReset = 0,
782 /// Bloc is reset.
783 BlocIsReset = 1
784 ],
785 /// GPIO secure reset control.
786 GPIO_SEC_RST OFFSET(29) NUMBITS(1) [
787 /// Bloc is not reset.
788 BlocIsNotReset = 0,
789 /// Bloc is reset.
790 BlocIsReset = 1
791 ],
792 /// GPIO secure int reset control.
793 GPIO_SEC_INT_RST OFFSET(30) NUMBITS(1) [
794 /// Bloc is not reset.
795 BlocIsNotReset = 0,
796 /// Bloc is reset.
797 BlocIsReset = 1
798 ]
799],
800PRESETCTRLX2 [
801 /// Data array value
802 DATA OFFSET(0) NUMBITS(32) []
803],
804SWR_RESET [
805 /// Write 0x5A00_0001 to generate a software_reset.
806 SWR_RESET OFFSET(0) NUMBITS(32) [
807 /// Bloc is not reset.
808 BlocIsNotReset = 0,
809 /// Generate a software reset.
810 GenerateASoftwareReset = 1509949441
811 ]
812],
813pub AHBCLKCTRL0 [
814 /// Enables the clock for the ROM.
815 ROM OFFSET(1) NUMBITS(1) [
816 /// Disable Clock.
817 DisableClock = 0,
818 /// Enable Clock.
819 EnableClock = 1
820 ],
821 /// Enables the clock for the SRAM Controller 1.
822 SRAM_CTRL1 OFFSET(3) NUMBITS(1) [
823 /// Disable Clock.
824 DisableClock = 0,
825 /// Enable Clock.
826 EnableClock = 1
827 ],
828 /// Enables the clock for the SRAM Controller 2.
829 SRAM_CTRL2 OFFSET(4) NUMBITS(1) [
830 /// Disable Clock.
831 DisableClock = 0,
832 /// Enable Clock.
833 EnableClock = 1
834 ],
835 /// Enables the clock for the SRAM Controller 3.
836 SRAM_CTRL3 OFFSET(5) NUMBITS(1) [
837 /// Disable Clock.
838 DisableClock = 0,
839 /// Enable Clock.
840 EnableClock = 1
841 ],
842 /// Enables the clock for the SRAM Controller 4.
843 SRAM_CTRL4 OFFSET(6) NUMBITS(1) [
844 /// Disable Clock.
845 DisableClock = 0,
846 /// Enable Clock.
847 EnableClock = 1
848 ],
849 /// Enables the clock for the Flash controller.
850 FLASH OFFSET(7) NUMBITS(1) [
851 /// Disable Clock.
852 DisableClock = 0,
853 /// Enable Clock.
854 EnableClock = 1
855 ],
856 /// Enables the clock for the FMC controller.
857 FMC OFFSET(8) NUMBITS(1) [
858 /// Disable Clock.
859 DisableClock = 0,
860 /// Enable Clock.
861 EnableClock = 1
862 ],
863 /// Enables the clock for the Input Mux.
864 MUX OFFSET(11) NUMBITS(1) [
865 /// Disable Clock.
866 DisableClock = 0,
867 /// Enable Clock.
868 EnableClock = 1
869 ],
870 /// Enables the clock for the I/O controller.
871 IOCON OFFSET(13) NUMBITS(1) [
872 /// Disable Clock.
873 DisableClock = 0,
874 /// Enable Clock.
875 EnableClock = 1
876 ],
877 /// Enables the clock for the GPIO0.
878 GPIO0 OFFSET(14) NUMBITS(1) [
879 /// Disable Clock.
880 DisableClock = 0,
881 /// Enable Clock.
882 EnableClock = 1
883 ],
884 /// Enables the clock for the GPIO1.
885 GPIO1 OFFSET(15) NUMBITS(1) [
886 /// Disable Clock.
887 DisableClock = 0,
888 /// Enable Clock.
889 EnableClock = 1
890 ],
891 /// Enables the clock for the GPIO2.
892 GPIO2 OFFSET(16) NUMBITS(1) [
893 /// Disable Clock.
894 DisableClock = 0,
895 /// Enable Clock.
896 EnableClock = 1
897 ],
898 /// Enables the clock for the GPIO3.
899 GPIO3 OFFSET(17) NUMBITS(1) [
900 /// Disable Clock.
901 DisableClock = 0,
902 /// Enable Clock.
903 EnableClock = 1
904 ],
905 /// Enables the clock for the Pin interrupt (PINT).
906 PINT OFFSET(18) NUMBITS(1) [
907 /// Disable Clock.
908 DisableClock = 0,
909 /// Enable Clock.
910 EnableClock = 1
911 ],
912 /// Enables the clock for the Group interrupt (GINT).
913 GINT OFFSET(19) NUMBITS(1) [
914 /// Disable Clock.
915 DisableClock = 0,
916 /// Enable Clock.
917 EnableClock = 1
918 ],
919 /// Enables the clock for the DMA0.
920 DMA0 OFFSET(20) NUMBITS(1) [
921 /// Disable Clock.
922 DisableClock = 0,
923 /// Enable Clock.
924 EnableClock = 1
925 ],
926 /// Enables the clock for the CRCGEN.
927 CRCGEN OFFSET(21) NUMBITS(1) [
928 /// Disable Clock.
929 DisableClock = 0,
930 /// Enable Clock.
931 EnableClock = 1
932 ],
933 /// Enables the clock for the Watchdog Timer.
934 WWDT OFFSET(22) NUMBITS(1) [
935 /// Disable Clock.
936 DisableClock = 0,
937 /// Enable Clock.
938 EnableClock = 1
939 ],
940 /// Enables the clock for the Real Time Clock (RTC).
941 RTC OFFSET(23) NUMBITS(1) [
942 /// Disable Clock.
943 DisableClock = 0,
944 /// Enable Clock.
945 EnableClock = 1
946 ],
947 /// Enables the clock for the Inter CPU communication Mailbox.
948 MAILBOX OFFSET(26) NUMBITS(1) [
949 /// Disable Clock.
950 DisableClock = 0,
951 /// Enable Clock.
952 EnableClock = 1
953 ],
954 /// Enables the clock for the ADC.
955 ADC OFFSET(27) NUMBITS(1) [
956 /// Disable Clock.
957 DisableClock = 0,
958 /// Enable Clock.
959 EnableClock = 1
960 ]
961],
962AHBCLKCTRLX0 [
963 /// Data array value
964 DATA OFFSET(0) NUMBITS(32) []
965],
966pub AHBCLKCTRL1 [
967 /// Enables the clock for the MRT.
968 MRT OFFSET(0) NUMBITS(1) [
969 /// Disable Clock.
970 DisableClock = 0,
971 /// Enable Clock.
972 EnableClock = 1
973 ],
974 /// Enables the clock for the OS Event Timer.
975 OSTIMER OFFSET(1) NUMBITS(1) [
976 /// Disable Clock.
977 DisableClock = 0,
978 /// Enable Clock.
979 EnableClock = 1
980 ],
981 /// Enables the clock for the SCT.
982 SCT OFFSET(2) NUMBITS(1) [
983 /// Disable Clock.
984 DisableClock = 0,
985 /// Enable Clock.
986 EnableClock = 1
987 ],
988 /// Enables the clock for the UTICK.
989 UTICK OFFSET(10) NUMBITS(1) [
990 /// Disable Clock.
991 DisableClock = 0,
992 /// Enable Clock.
993 EnableClock = 1
994 ],
995 /// Enables the clock for the FC0.
996 FC0 OFFSET(11) NUMBITS(1) [
997 /// Disable Clock.
998 DisableClock = 0,
999 /// Enable Clock.
1000 EnableClock = 1
1001 ],
1002 /// Enables the clock for the FC1.
1003 FC1 OFFSET(12) NUMBITS(1) [
1004 /// Disable Clock.
1005 DisableClock = 0,
1006 /// Enable Clock.
1007 EnableClock = 1
1008 ],
1009 /// Enables the clock for the FC2.
1010 FC2 OFFSET(13) NUMBITS(1) [
1011 /// Disable Clock.
1012 DisableClock = 0,
1013 /// Enable Clock.
1014 EnableClock = 1
1015 ],
1016 /// Enables the clock for the FC3.
1017 FC3 OFFSET(14) NUMBITS(1) [
1018 /// Disable Clock.
1019 DisableClock = 0,
1020 /// Enable Clock.
1021 EnableClock = 1
1022 ],
1023 /// Enables the clock for the FC4.
1024 FC4 OFFSET(15) NUMBITS(1) [
1025 /// Disable Clock.
1026 DisableClock = 0,
1027 /// Enable Clock.
1028 EnableClock = 1
1029 ],
1030 /// Enables the clock for the FC5.
1031 FC5 OFFSET(16) NUMBITS(1) [
1032 /// Disable Clock.
1033 DisableClock = 0,
1034 /// Enable Clock.
1035 EnableClock = 1
1036 ],
1037 /// Enables the clock for the FC6.
1038 FC6 OFFSET(17) NUMBITS(1) [
1039 /// Disable Clock.
1040 DisableClock = 0,
1041 /// Enable Clock.
1042 EnableClock = 1
1043 ],
1044 /// Enables the clock for the FC7.
1045 FC7 OFFSET(18) NUMBITS(1) [
1046 /// Disable Clock.
1047 DisableClock = 0,
1048 /// Enable Clock.
1049 EnableClock = 1
1050 ],
1051 /// Enables the clock for the Timer 2.
1052 TIMER2 OFFSET(22) NUMBITS(1) [
1053 /// Disable Clock.
1054 DisableClock = 0,
1055 /// Enable Clock.
1056 EnableClock = 1
1057 ],
1058 /// Enables the clock for the USB0 DEV.
1059 USB0_DEV OFFSET(25) NUMBITS(1) [
1060 /// Disable Clock.
1061 DisableClock = 0,
1062 /// Enable Clock.
1063 EnableClock = 1
1064 ],
1065 /// Enables the clock for the Timer 0.
1066 TIMER0 OFFSET(26) NUMBITS(1) [
1067 /// Disable Clock.
1068 DisableClock = 0,
1069 /// Enable Clock.
1070 EnableClock = 1
1071 ],
1072 /// Enables the clock for the Timer 1.
1073 TIMER1 OFFSET(27) NUMBITS(1) [
1074 /// Disable Clock.
1075 DisableClock = 0,
1076 /// Enable Clock.
1077 EnableClock = 1
1078 ]
1079],
1080AHBCLKCTRLX1 [
1081 /// Data array value
1082 DATA OFFSET(0) NUMBITS(32) []
1083],
1084AHBCLKCTRL2 [
1085 /// Enables the clock for the DMA1.
1086 DMA1 OFFSET(1) NUMBITS(1) [
1087 /// Disable Clock.
1088 DisableClock = 0,
1089 /// Enable Clock.
1090 EnableClock = 1
1091 ],
1092 /// Enables the clock for the Comparator.
1093 COMP OFFSET(2) NUMBITS(1) [
1094 /// Disable Clock.
1095 DisableClock = 0,
1096 /// Enable Clock.
1097 EnableClock = 1
1098 ],
1099 /// Enables the clock for the SDIO.
1100 SDIO OFFSET(3) NUMBITS(1) [
1101 /// Disable Clock.
1102 DisableClock = 0,
1103 /// Enable Clock.
1104 EnableClock = 1
1105 ],
1106 /// Enables the clock for the USB1 Host.
1107 USB1_HOST OFFSET(4) NUMBITS(1) [
1108 /// Disable Clock.
1109 DisableClock = 0,
1110 /// Enable Clock.
1111 EnableClock = 1
1112 ],
1113 /// Enables the clock for the USB1 dev.
1114 USB1_DEV OFFSET(5) NUMBITS(1) [
1115 /// Disable Clock.
1116 DisableClock = 0,
1117 /// Enable Clock.
1118 EnableClock = 1
1119 ],
1120 /// Enables the clock for the USB1 RAM.
1121 USB1_RAM OFFSET(6) NUMBITS(1) [
1122 /// Disable Clock.
1123 DisableClock = 0,
1124 /// Enable Clock.
1125 EnableClock = 1
1126 ],
1127 /// Enables the clock for the USB1 PHY.
1128 USB1_PHY OFFSET(7) NUMBITS(1) [
1129 /// Disable Clock.
1130 DisableClock = 0,
1131 /// Enable Clock.
1132 EnableClock = 1
1133 ],
1134 /// Enables the clock for the Frequency meter.
1135 FREQME OFFSET(8) NUMBITS(1) [
1136 /// Disable Clock.
1137 DisableClock = 0,
1138 /// Enable Clock.
1139 EnableClock = 1
1140 ],
1141 /// Enables the clock for the RNG.
1142 RNG OFFSET(13) NUMBITS(1) [
1143 /// Disable Clock.
1144 DisableClock = 0,
1145 /// Enable Clock.
1146 EnableClock = 1
1147 ],
1148 /// SYSCTL block clock.
1149 SYSCTL OFFSET(15) NUMBITS(1) [
1150 /// Disable Clock.
1151 DisableClock = 0,
1152 /// Enable Clock.
1153 EnableClock = 1
1154 ],
1155 /// Enables the clock for the USB0 Host Master.
1156 USB0_HOSTM OFFSET(16) NUMBITS(1) [
1157 /// Disable Clock.
1158 DisableClock = 0,
1159 /// Enable Clock.
1160 EnableClock = 1
1161 ],
1162 /// Enables the clock for the USB0 Host Slave.
1163 USB0_HOSTS OFFSET(17) NUMBITS(1) [
1164 /// Disable Clock.
1165 DisableClock = 0,
1166 /// Enable Clock.
1167 EnableClock = 1
1168 ],
1169 /// Enables the clock for the HASH_AES.
1170 HASH_AES OFFSET(18) NUMBITS(1) [
1171 /// Disable Clock.
1172 DisableClock = 0,
1173 /// Enable Clock.
1174 EnableClock = 1
1175 ],
1176 /// Enables the clock for the Power Quad.
1177 PQ OFFSET(19) NUMBITS(1) [
1178 /// Disable Clock.
1179 DisableClock = 0,
1180 /// Enable Clock.
1181 EnableClock = 1
1182 ],
1183 /// Enables the clock for the PLU LUT.
1184 PLULUT OFFSET(20) NUMBITS(1) [
1185 /// Disable Clock.
1186 DisableClock = 0,
1187 /// Enable Clock.
1188 EnableClock = 1
1189 ],
1190 /// Enables the clock for the Timer 3.
1191 TIMER3 OFFSET(21) NUMBITS(1) [
1192 /// Disable Clock.
1193 DisableClock = 0,
1194 /// Enable Clock.
1195 EnableClock = 1
1196 ],
1197 /// Enables the clock for the Timer 4.
1198 TIMER4 OFFSET(22) NUMBITS(1) [
1199 /// Disable Clock.
1200 DisableClock = 0,
1201 /// Enable Clock.
1202 EnableClock = 1
1203 ],
1204 /// Enables the clock for the PUF reset control.
1205 PUF OFFSET(23) NUMBITS(1) [
1206 /// Disable Clock.
1207 DisableClock = 0,
1208 /// Enable Clock.
1209 EnableClock = 1
1210 ],
1211 /// Enables the clock for the Casper.
1212 CASPER OFFSET(24) NUMBITS(1) [
1213 /// Disable Clock.
1214 DisableClock = 0,
1215 /// Enable Clock.
1216 EnableClock = 1
1217 ],
1218 /// Enables the clock for the analog control.
1219 ANALOG_CTRL OFFSET(27) NUMBITS(1) [
1220 /// Disable Clock.
1221 DisableClock = 0,
1222 /// Enable Clock.
1223 EnableClock = 1
1224 ],
1225 /// Enables the clock for the HS LSPI.
1226 HS_LSPI OFFSET(28) NUMBITS(1) [
1227 /// Disable Clock.
1228 DisableClock = 0,
1229 /// Enable Clock.
1230 EnableClock = 1
1231 ],
1232 /// Enables the clock for the GPIO secure.
1233 GPIO_SEC OFFSET(29) NUMBITS(1) [
1234 /// Disable Clock.
1235 DisableClock = 0,
1236 /// Enable Clock.
1237 EnableClock = 1
1238 ],
1239 /// Enables the clock for the GPIO secure int.
1240 GPIO_SEC_INT OFFSET(30) NUMBITS(1) [
1241 /// Disable Clock.
1242 DisableClock = 0,
1243 /// Enable Clock.
1244 EnableClock = 1
1245 ]
1246],
1247AHBCLKCTRLX2 [
1248 /// Data array value
1249 DATA OFFSET(0) NUMBITS(32) []
1250],
1251SYSTICKCLKSEL0 [
1252 /// System Tick Timer for CPU0 source select.
1253 SEL OFFSET(0) NUMBITS(3) [
1254 /// System Tick 0 divided clock.
1255 SystemTick0DividedClock = 0,
1256 /// FRO 1MHz clock.
1257 FRO1MHzClock = 1,
1258 /// Oscillator 32 kHz clock.
1259 Oscillator32KHzClock = 2,
1260 /// No clock.
1261 NoClock = 3
1262 ]
1263],
1264SYSTICKCLKSELX0 [
1265 /// Data array value
1266 DATA OFFSET(0) NUMBITS(32) []
1267],
1268SYSTICKCLKSEL1 [
1269 /// System Tick Timer for CPU1 source select.
1270 SEL OFFSET(0) NUMBITS(3) [
1271 /// System Tick 1 divided clock.
1272 SystemTick1DividedClock = 0,
1273 /// FRO 1MHz clock.
1274 FRO1MHzClock = 1,
1275 /// Oscillator 32 kHz clock.
1276 Oscillator32KHzClock = 2,
1277 /// No clock.
1278 NoClock = 3
1279 ]
1280],
1281SYSTICKCLKSELX1 [
1282 /// Data array value
1283 DATA OFFSET(0) NUMBITS(32) []
1284],
1285TRACECLKSEL [
1286 /// Trace clock source select.
1287 SEL OFFSET(0) NUMBITS(3) [
1288 /// Trace divided clock.
1289 TraceDividedClock = 0,
1290 /// FRO 1MHz clock.
1291 FRO1MHzClock = 1,
1292 /// Oscillator 32 kHz clock.
1293 Oscillator32KHzClock = 2,
1294 /// No clock.
1295 NoClock = 3
1296 ]
1297],
1298pub CTIMERCLKSEL0 [
1299 /// CTimer 0 clock source select.
1300 SEL OFFSET(0) NUMBITS(3) [
1301 /// Main clock.
1302 MainClock = 0,
1303 /// PLL0 clock.
1304 PLL0Clock = 1,
1305 /// No clock.
1306 NoClock = 2,
1307 /// FRO 96 MHz clock.
1308 FRO96MHzClock = 3,
1309 /// FRO 1MHz clock.
1310 FRO1MHzClock = 4,
1311 /// MCLK clock.
1312 MCLKClock = 5,
1313 /// Oscillator 32kHz clock.
1314 Oscillator32kHzClock = 6
1315 ]
1316],
1317CTIMERCLKSELX0 [
1318 /// Data array value
1319 DATA OFFSET(0) NUMBITS(32) []
1320],
1321CTIMERCLKSEL1 [
1322 /// CTimer 1 clock source select.
1323 SEL OFFSET(0) NUMBITS(3) [
1324 /// Main clock.
1325 MainClock = 0,
1326 /// PLL0 clock.
1327 PLL0Clock = 1,
1328 /// No clock.
1329 NoClock = 2,
1330 /// FRO 96 MHz clock.
1331 FRO96MHzClock = 3,
1332 /// FRO 1MHz clock.
1333 FRO1MHzClock = 4,
1334 /// MCLK clock.
1335 MCLKClock = 5,
1336 /// Oscillator 32kHz clock.
1337 Oscillator32kHzClock = 6
1338 ]
1339],
1340CTIMERCLKSELX1 [
1341 /// Data array value
1342 DATA OFFSET(0) NUMBITS(32) []
1343],
1344CTIMERCLKSEL2 [
1345 /// CTimer 2 clock source select.
1346 SEL OFFSET(0) NUMBITS(3) [
1347 /// Main clock.
1348 MainClock = 0,
1349 /// PLL0 clock.
1350 PLL0Clock = 1,
1351 /// No clock.
1352 NoClock = 2,
1353 /// FRO 96 MHz clock.
1354 FRO96MHzClock = 3,
1355 /// FRO 1MHz clock.
1356 FRO1MHzClock = 4,
1357 /// MCLK clock.
1358 MCLKClock = 5,
1359 /// Oscillator 32kHz clock.
1360 Oscillator32kHzClock = 6
1361 ]
1362],
1363CTIMERCLKSELX2 [
1364 /// Data array value
1365 DATA OFFSET(0) NUMBITS(32) []
1366],
1367CTIMERCLKSEL3 [
1368 /// CTimer 3 clock source select.
1369 SEL OFFSET(0) NUMBITS(3) [
1370 /// Main clock.
1371 MainClock = 0,
1372 /// PLL0 clock.
1373 PLL0Clock = 1,
1374 /// No clock.
1375 NoClock = 2,
1376 /// FRO 96 MHz clock.
1377 FRO96MHzClock = 3,
1378 /// FRO 1MHz clock.
1379 FRO1MHzClock = 4,
1380 /// MCLK clock.
1381 MCLKClock = 5,
1382 /// Oscillator 32kHz clock.
1383 Oscillator32kHzClock = 6
1384 ]
1385],
1386CTIMERCLKSELX3 [
1387 /// Data array value
1388 DATA OFFSET(0) NUMBITS(32) []
1389],
1390CTIMERCLKSEL4 [
1391 /// CTimer 4 clock source select.
1392 SEL OFFSET(0) NUMBITS(3) [
1393 /// Main clock.
1394 MainClock = 0,
1395 /// PLL0 clock.
1396 PLL0Clock = 1,
1397 /// No clock.
1398 NoClock = 2,
1399 /// FRO 96 MHz clock.
1400 FRO96MHzClock = 3,
1401 /// FRO 1MHz clock.
1402 FRO1MHzClock = 4,
1403 /// MCLK clock.
1404 MCLKClock = 5,
1405 /// Oscillator 32kHz clock.
1406 Oscillator32kHzClock = 6
1407 ]
1408],
1409CTIMERCLKSELX4 [
1410 /// Data array value
1411 DATA OFFSET(0) NUMBITS(32) []
1412],
1413MAINCLKSELA [
1414 /// Main clock A source select.
1415 SEL OFFSET(0) NUMBITS(3) [
1416 /// FRO 12 MHz clock.
1417 FRO12MHzClock = 0,
1418 /// CLKIN clock.
1419 CLKINClock = 1,
1420 /// FRO 1MHz clock.
1421 FRO1MHzClock = 2,
1422 /// FRO 96 MHz clock.
1423 FRO96MHzClock = 3
1424 ]
1425],
1426MAINCLKSELB [
1427 /// Main clock source select.
1428 SEL OFFSET(0) NUMBITS(3) [
1429 /// Main Clock A.
1430 MainClockA = 0,
1431 /// PLL0 clock.
1432 PLL0Clock = 1,
1433 /// PLL1 clock.
1434 PLL1Clock = 2,
1435 /// Oscillator 32 kHz clock.
1436 Oscillator32KHzClock = 3
1437 ]
1438],
1439pub CLKOUTSEL [
1440 /// CLKOUT clock source select.
1441 SEL OFFSET(0) NUMBITS(3) [
1442 /// Main clock.
1443 MainClock = 0,
1444 /// PLL0 clock.
1445 PLL0Clock = 1,
1446 /// CLKIN clock.
1447 CLKINClock = 2,
1448 /// FRO 96 MHz clock.
1449 FRO96MHzClock = 3,
1450 /// FRO 1MHz clock.
1451 FRO1MHzClock = 4,
1452 /// PLL1 clock.
1453 PLL1Clock = 5,
1454 /// Oscillator 32kHz clock.
1455 Oscillator32kHzClock = 6,
1456 /// No clock.
1457 NoClock = 7
1458 ]
1459],
1460PLL0CLKSEL [
1461 /// PLL0 clock source select.
1462 SEL OFFSET(0) NUMBITS(3) [
1463 /// FRO 12 MHz clock.
1464 FRO12MHzClock = 0,
1465 /// CLKIN clock.
1466 CLKINClock = 1,
1467 /// FRO 1MHz clock.
1468 FRO1MHzClock = 2,
1469 /// Oscillator 32kHz clock.
1470 Oscillator32kHzClock = 3,
1471 /// No clock.
1472 NoClock = 4
1473 ]
1474],
1475PLL1CLKSEL [
1476 /// PLL1 clock source select.
1477 SEL OFFSET(0) NUMBITS(3) [
1478 /// FRO 12 MHz clock.
1479 FRO12MHzClock = 0,
1480 /// CLKIN clock.
1481 CLKINClock = 1,
1482 /// FRO 1MHz clock.
1483 FRO1MHzClock = 2,
1484 /// Oscillator 32kHz clock.
1485 Oscillator32kHzClock = 3,
1486 /// No clock.
1487 NoClock = 4
1488 ]
1489],
1490ADCCLKSEL [
1491 /// ADC clock source select.
1492 SEL OFFSET(0) NUMBITS(3) [
1493 /// Main clock.
1494 MainClock = 0,
1495 /// PLL0 clock.
1496 PLL0Clock = 1,
1497 /// FRO 96 MHz clock.
1498 FRO96MHzClock = 2,
1499 /// No clock.
1500 NoClock = 4
1501 ]
1502],
1503USB0CLKSEL [
1504 /// FS USB clock source select.
1505 SEL OFFSET(0) NUMBITS(3) [
1506 /// Main clock.
1507 MainClock = 0,
1508 /// PLL0 clock.
1509 PLL0Clock = 1,
1510 /// No clock.
1511 NoClock = 2,
1512 /// FRO 96 MHz clock.
1513 FRO96MHzClock = 3,
1514 /// PLL1 clock.
1515 PLL1Clock = 5
1516 ]
1517],
1518pub FCCLKSEL [
1519 /// Flexcomm Interface 0 clock source select for Fractional Rate Divider.
1520 SEL OFFSET(0) NUMBITS(3) [
1521 /// Main clock.
1522 MainClock = 0,
1523 /// system PLL divided clock.
1524 SystemPLLDividedClock = 1,
1525 /// FRO 12 MHz clock.
1526 FRO12MHzClock = 2,
1527 /// FRO 96 MHz clock.
1528 FRO96MHzClock = 3,
1529 /// FRO 1MHz clock.
1530 FRO1MHzClock = 4,
1531 /// MCLK clock.
1532 MCLKClock = 5,
1533 /// Oscillator 32 kHz clock.
1534 Oscillator32KHzClock = 6,
1535 /// No clock.
1536 NoClock = 7
1537 ]
1538],
1539FCCLKSELX0 [
1540 /// Data array value
1541 DATA OFFSET(0) NUMBITS(32) []
1542],
1543pub FCCLKSEL1 [
1544 /// Flexcomm Interface 1 clock source select for Fractional Rate Divider.
1545 SEL OFFSET(0) NUMBITS(3) [
1546 /// Main clock.
1547 MainClock = 0,
1548 /// system PLL divided clock.
1549 SystemPLLDividedClock = 1,
1550 /// FRO 12 MHz clock.
1551 FRO12MHzClock = 2,
1552 /// FRO 96 MHz clock.
1553 FRO96MHzClock = 3,
1554 /// FRO 1MHz clock.
1555 FRO1MHzClock = 4,
1556 /// MCLK clock.
1557 MCLKClock = 5,
1558 /// Oscillator 32 kHz clock.
1559 Oscillator32KHzClock = 6,
1560 /// No clock.
1561 NoClock = 7
1562 ]
1563],
1564FCCLKSELX1 [
1565 /// Data array value
1566 DATA OFFSET(0) NUMBITS(32) []
1567],
1568pub FCCLKSEL2 [
1569 /// Flexcomm Interface 2 clock source select for Fractional Rate Divider.
1570 SEL OFFSET(0) NUMBITS(3) [
1571 /// Main clock.
1572 MainClock = 0,
1573 /// system PLL divided clock.
1574 SystemPLLDividedClock = 1,
1575 /// FRO 12 MHz clock.
1576 FRO12MHzClock = 2,
1577 /// FRO 96 MHz clock.
1578 FRO96MHzClock = 3,
1579 /// FRO 1MHz clock.
1580 FRO1MHzClock = 4,
1581 /// MCLK clock.
1582 MCLKClock = 5,
1583 /// Oscillator 32 kHz clock.
1584 Oscillator32KHzClock = 6,
1585 /// No clock.
1586 NoClock = 7
1587 ]
1588],
1589FCCLKSELX2 [
1590 /// Data array value
1591 DATA OFFSET(0) NUMBITS(32) []
1592],
1593pub FCCLKSEL3 [
1594 /// Flexcomm Interface 3 clock source select for Fractional Rate Divider.
1595 SEL OFFSET(0) NUMBITS(3) [
1596 /// Main clock.
1597 MainClock = 0,
1598 /// system PLL divided clock.
1599 SystemPLLDividedClock = 1,
1600 /// FRO 12 MHz clock.
1601 FRO12MHzClock = 2,
1602 /// FRO 96 MHz clock.
1603 FRO96MHzClock = 3,
1604 /// FRO 1MHz clock.
1605 FRO1MHzClock = 4,
1606 /// MCLK clock.
1607 MCLKClock = 5,
1608 /// Oscillator 32 kHz clock.
1609 Oscillator32KHzClock = 6,
1610 /// No clock.
1611 NoClock = 7
1612 ]
1613],
1614FCCLKSELX3 [
1615 /// Data array value
1616 DATA OFFSET(0) NUMBITS(32) []
1617],
1618pub FCCLKSEL4 [
1619 /// Flexcomm Interface 4 clock source select for Fractional Rate Divider.
1620 SEL OFFSET(0) NUMBITS(3) [
1621 /// Main clock.
1622 MainClock = 0,
1623 /// system PLL divided clock.
1624 SystemPLLDividedClock = 1,
1625 /// FRO 12 MHz clock.
1626 FRO12MHzClock = 2,
1627 /// FRO 96 MHz clock.
1628 FRO96MHzClock = 3,
1629 /// FRO 1MHz clock.
1630 FRO1MHzClock = 4,
1631 /// MCLK clock.
1632 MCLKClock = 5,
1633 /// Oscillator 32 kHz clock.
1634 Oscillator32KHzClock = 6,
1635 /// No clock.
1636 NoClock = 7
1637 ]
1638],
1639FCCLKSELX4 [
1640 /// Data array value
1641 DATA OFFSET(0) NUMBITS(32) []
1642],
1643pub FCCLKSEL5 [
1644 /// Flexcomm Interface 5 clock source select for Fractional Rate Divider.
1645 SEL OFFSET(0) NUMBITS(3) [
1646 /// Main clock.
1647 MainClock = 0,
1648 /// system PLL divided clock.
1649 SystemPLLDividedClock = 1,
1650 /// FRO 12 MHz clock.
1651 FRO12MHzClock = 2,
1652 /// FRO 96 MHz clock.
1653 FRO96MHzClock = 3,
1654 /// FRO 1MHz clock.
1655 FRO1MHzClock = 4,
1656 /// MCLK clock.
1657 MCLKClock = 5,
1658 /// Oscillator 32 kHz clock.
1659 Oscillator32KHzClock = 6,
1660 /// No clock.
1661 NoClock = 7
1662 ]
1663],
1664FCCLKSELX5 [
1665 /// Data array value
1666 DATA OFFSET(0) NUMBITS(32) []
1667],
1668pub FCCLKSEL6 [
1669 /// Flexcomm Interface 6 clock source select for Fractional Rate Divider.
1670 SEL OFFSET(0) NUMBITS(3) [
1671 /// Main clock.
1672 MainClock = 0,
1673 /// system PLL divided clock.
1674 SystemPLLDividedClock = 1,
1675 /// FRO 12 MHz clock.
1676 FRO12MHzClock = 2,
1677 /// FRO 96 MHz clock.
1678 FRO96MHzClock = 3,
1679 /// FRO 1MHz clock.
1680 FRO1MHzClock = 4,
1681 /// MCLK clock.
1682 MCLKClock = 5,
1683 /// Oscillator 32 kHz clock.
1684 Oscillator32KHzClock = 6,
1685 /// No clock.
1686 NoClock = 7
1687 ]
1688],
1689FCCLKSELX6 [
1690 /// Data array value
1691 DATA OFFSET(0) NUMBITS(32) []
1692],
1693pub FCCLKSEL7 [
1694 /// Flexcomm Interface 7 clock source select for Fractional Rate Divider.
1695 SEL OFFSET(0) NUMBITS(3) [
1696 /// Main clock.
1697 MainClock = 0,
1698 /// system PLL divided clock.
1699 SystemPLLDividedClock = 1,
1700 /// FRO 12 MHz clock.
1701 FRO12MHzClock = 2,
1702 /// FRO 96 MHz clock.
1703 FRO96MHzClock = 3,
1704 /// FRO 1MHz clock.
1705 FRO1MHzClock = 4,
1706 /// MCLK clock.
1707 MCLKClock = 5,
1708 /// Oscillator 32 kHz clock.
1709 Oscillator32KHzClock = 6,
1710 /// No clock.
1711 NoClock = 7
1712 ]
1713],
1714FCCLKSELX7 [
1715 /// Data array value
1716 DATA OFFSET(0) NUMBITS(32) []
1717],
1718HSLSPICLKSEL [
1719 /// HS LSPI clock source select.
1720 SEL OFFSET(0) NUMBITS(3) [
1721 /// Main clock.
1722 MainClock = 0,
1723 /// system PLL divided clock.
1724 SystemPLLDividedClock = 1,
1725 /// FRO 12 MHz clock.
1726 FRO12MHzClock = 2,
1727 /// FRO 96 MHz clock.
1728 FRO96MHzClock = 3,
1729 /// FRO 1MHz clock.
1730 FRO1MHzClock = 4,
1731 /// No clock.
1732 NoClock = 5,
1733 /// Oscillator 32 kHz clock.
1734 Oscillator32KHzClock = 6
1735 ]
1736],
1737MCLKCLKSEL [
1738 /// MCLK clock source select.
1739 SEL OFFSET(0) NUMBITS(3) [
1740 /// FRO 96 MHz clock.
1741 FRO96MHzClock = 0,
1742 /// PLL0 clock.
1743 PLL0Clock = 1,
1744 /// No clock.
1745 NoClock = 4
1746 ]
1747],
1748SCTCLKSEL [
1749 /// SCTimer/PWM clock source select.
1750 SEL OFFSET(0) NUMBITS(3) [
1751 /// Main clock.
1752 MainClock = 0,
1753 /// PLL0 clock.
1754 PLL0Clock = 1,
1755 /// CLKIN clock.
1756 CLKINClock = 2,
1757 /// FRO 96 MHz clock.
1758 FRO96MHzClock = 3,
1759 /// No clock.
1760 NoClock = 4,
1761 /// MCLK clock.
1762 MCLKClock = 5
1763 ]
1764],
1765SDIOCLKSEL [
1766 /// SDIO clock source select.
1767 SEL OFFSET(0) NUMBITS(3) [
1768 /// Main clock.
1769 MainClock = 0,
1770 /// PLL0 clock.
1771 PLL0Clock = 1,
1772 /// No clock.
1773 NoClock = 2,
1774 /// FRO 96 MHz clock.
1775 FRO96MHzClock = 3,
1776 /// PLL1 clock.
1777 PLL1Clock = 5
1778 ]
1779],
1780SYSTICKCLKDIV0 [
1781 /// Clock divider value.
1782 DIV OFFSET(0) NUMBITS(8) [],
1783 /// Resets the divider counter.
1784 RESET OFFSET(29) NUMBITS(1) [
1785 /// Divider is not reset.
1786 DividerIsNotReset = 0,
1787 /// Divider is reset.
1788 DividerIsReset = 1
1789 ],
1790 /// Halts the divider counter.
1791 HALT OFFSET(30) NUMBITS(1) [
1792 /// Divider clock is running.
1793 DividerClockIsRunning = 0,
1794 /// Divider clock is stoped.
1795 DividerClockIsStoped = 1
1796 ],
1797 /// Divider status flag.
1798 REQFLAG OFFSET(31) NUMBITS(1) [
1799 /// Divider clock is stable.
1800 DividerClockIsStable = 0,
1801 /// Clock frequency is not stable.
1802 ClockFrequencyIsNotStable = 1
1803 ]
1804],
1805SYSTICKCLKDIV1 [
1806 /// Clock divider value.
1807 DIV OFFSET(0) NUMBITS(8) [],
1808 /// Resets the divider counter.
1809 RESET OFFSET(29) NUMBITS(1) [
1810 /// Divider is not reset.
1811 DividerIsNotReset = 0,
1812 /// Divider is reset.
1813 DividerIsReset = 1
1814 ],
1815 /// Halts the divider counter.
1816 HALT OFFSET(30) NUMBITS(1) [
1817 /// Divider clock is running.
1818 DividerClockIsRunning = 0,
1819 /// Divider clock is stoped.
1820 DividerClockIsStoped = 1
1821 ],
1822 /// Divider status flag.
1823 REQFLAG OFFSET(31) NUMBITS(1) [
1824 /// Divider clock is stable.
1825 DividerClockIsStable = 0,
1826 /// Clock frequency is not stable.
1827 ClockFrequencyIsNotStable = 1
1828 ]
1829],
1830TRACECLKDIV [
1831 /// Clock divider value.
1832 DIV OFFSET(0) NUMBITS(8) [],
1833 /// Resets the divider counter.
1834 RESET OFFSET(29) NUMBITS(1) [
1835 /// Divider is not reset.
1836 DividerIsNotReset = 0,
1837 /// Divider is reset.
1838 DividerIsReset = 1
1839 ],
1840 /// Halts the divider counter.
1841 HALT OFFSET(30) NUMBITS(1) [
1842 /// Divider clock is running.
1843 DividerClockIsRunning = 0,
1844 /// Divider clock is stoped.
1845 DividerClockIsStoped = 1
1846 ],
1847 /// Divider status flag.
1848 REQFLAG OFFSET(31) NUMBITS(1) [
1849 /// Divider clock is stable.
1850 DividerClockIsStable = 0,
1851 /// Clock frequency is not stable.
1852 ClockFrequencyIsNotStable = 1
1853 ]
1854],
1855FLEXFRG0CTRL [
1856 /// Denominator of the fractional rate divider.
1857 DIV OFFSET(0) NUMBITS(8) [],
1858 /// Numerator of the fractional rate divider.
1859 MULT OFFSET(8) NUMBITS(8) []
1860],
1861FLEXFRGXCTRL0 [
1862 /// Data array value
1863 DATA OFFSET(0) NUMBITS(32) []
1864],
1865FLEXFRG1CTRL [
1866 /// Denominator of the fractional rate divider.
1867 DIV OFFSET(0) NUMBITS(8) [],
1868 /// Numerator of the fractional rate divider.
1869 MULT OFFSET(8) NUMBITS(8) []
1870],
1871FLEXFRGXCTRL1 [
1872 /// Data array value
1873 DATA OFFSET(0) NUMBITS(32) []
1874],
1875FLEXFRG2CTRL [
1876 /// Denominator of the fractional rate divider.
1877 DIV OFFSET(0) NUMBITS(8) [],
1878 /// Numerator of the fractional rate divider.
1879 MULT OFFSET(8) NUMBITS(8) []
1880],
1881FLEXFRGXCTRL2 [
1882 /// Data array value
1883 DATA OFFSET(0) NUMBITS(32) []
1884],
1885FLEXFRG3CTRL [
1886 /// Denominator of the fractional rate divider.
1887 DIV OFFSET(0) NUMBITS(8) [],
1888 /// Numerator of the fractional rate divider.
1889 MULT OFFSET(8) NUMBITS(8) []
1890],
1891FLEXFRGXCTRL3 [
1892 /// Data array value
1893 DATA OFFSET(0) NUMBITS(32) []
1894],
1895FLEXFRG4CTRL [
1896 /// Denominator of the fractional rate divider.
1897 DIV OFFSET(0) NUMBITS(8) [],
1898 /// Numerator of the fractional rate divider.
1899 MULT OFFSET(8) NUMBITS(8) []
1900],
1901FLEXFRGXCTRL4 [
1902 /// Data array value
1903 DATA OFFSET(0) NUMBITS(32) []
1904],
1905FLEXFRG5CTRL [
1906 /// Denominator of the fractional rate divider.
1907 DIV OFFSET(0) NUMBITS(8) [],
1908 /// Numerator of the fractional rate divider.
1909 MULT OFFSET(8) NUMBITS(8) []
1910],
1911FLEXFRGXCTRL5 [
1912 /// Data array value
1913 DATA OFFSET(0) NUMBITS(32) []
1914],
1915FLEXFRG6CTRL [
1916 /// Denominator of the fractional rate divider.
1917 DIV OFFSET(0) NUMBITS(8) [],
1918 /// Numerator of the fractional rate divider.
1919 MULT OFFSET(8) NUMBITS(8) []
1920],
1921FLEXFRGXCTRL6 [
1922 /// Data array value
1923 DATA OFFSET(0) NUMBITS(32) []
1924],
1925FLEXFRG7CTRL [
1926 /// Denominator of the fractional rate divider.
1927 DIV OFFSET(0) NUMBITS(8) [],
1928 /// Numerator of the fractional rate divider.
1929 MULT OFFSET(8) NUMBITS(8) []
1930],
1931FLEXFRGXCTRL7 [
1932 /// Data array value
1933 DATA OFFSET(0) NUMBITS(32) []
1934],
1935AHBCLKDIV [
1936 /// Clock divider value.
1937 DIV OFFSET(0) NUMBITS(8) [],
1938 /// Resets the divider counter.
1939 RESET OFFSET(29) NUMBITS(1) [
1940 /// Divider is not reset.
1941 DividerIsNotReset = 0,
1942 /// Divider is reset.
1943 DividerIsReset = 1
1944 ],
1945 /// Halts the divider counter.
1946 HALT OFFSET(30) NUMBITS(1) [
1947 /// Divider clock is running.
1948 DividerClockIsRunning = 0,
1949 /// Divider clock is stoped.
1950 DividerClockIsStoped = 1
1951 ],
1952 /// Divider status flag.
1953 REQFLAG OFFSET(31) NUMBITS(1) [
1954 /// Divider clock is stable.
1955 DividerClockIsStable = 0,
1956 /// Clock frequency is not stable.
1957 ClockFrequencyIsNotStable = 1
1958 ]
1959],
1960CLKOUTDIV [
1961 /// Clock divider value.
1962 DIV OFFSET(0) NUMBITS(8) [],
1963 /// Resets the divider counter.
1964 RESET OFFSET(29) NUMBITS(1) [
1965 /// Divider is not reset.
1966 DividerIsNotReset = 0,
1967 /// Divider is reset.
1968 DividerIsReset = 1
1969 ],
1970 /// Halts the divider counter.
1971 HALT OFFSET(30) NUMBITS(1) [
1972 /// Divider clock is running.
1973 DividerClockIsRunning = 0,
1974 /// Divider clock is stoped.
1975 DividerClockIsStoped = 1
1976 ],
1977 /// Divider status flag.
1978 REQFLAG OFFSET(31) NUMBITS(1) [
1979 /// Divider clock is stable.
1980 DividerClockIsStable = 0,
1981 /// Clock frequency is not stable.
1982 ClockFrequencyIsNotStable = 1
1983 ]
1984],
1985FROHFDIV [
1986 /// Clock divider value.
1987 DIV OFFSET(0) NUMBITS(8) [],
1988 /// Resets the divider counter.
1989 RESET OFFSET(29) NUMBITS(1) [
1990 /// Divider is not reset.
1991 DividerIsNotReset = 0,
1992 /// Divider is reset.
1993 DividerIsReset = 1
1994 ],
1995 /// Halts the divider counter.
1996 HALT OFFSET(30) NUMBITS(1) [
1997 /// Divider clock is running.
1998 DividerClockIsRunning = 0,
1999 /// Divider clock is stoped.
2000 DividerClockIsStoped = 1
2001 ],
2002 /// Divider status flag.
2003 REQFLAG OFFSET(31) NUMBITS(1) [
2004 /// Divider clock is stable.
2005 DividerClockIsStable = 0,
2006 /// Clock frequency is not stable.
2007 ClockFrequencyIsNotStable = 1
2008 ]
2009],
2010WDTCLKDIV [
2011 /// Clock divider value.
2012 DIV OFFSET(0) NUMBITS(6) [],
2013 /// Resets the divider counter.
2014 RESET OFFSET(29) NUMBITS(1) [
2015 /// Divider is not reset.
2016 DividerIsNotReset = 0,
2017 /// Divider is reset.
2018 DividerIsReset = 1
2019 ],
2020 /// Halts the divider counter.
2021 HALT OFFSET(30) NUMBITS(1) [
2022 /// Divider clock is running.
2023 DividerClockIsRunning = 0,
2024 /// Divider clock is stoped.
2025 DividerClockIsStoped = 1
2026 ],
2027 /// Divider status flag.
2028 REQFLAG OFFSET(31) NUMBITS(1) [
2029 /// Divider clock is stable.
2030 DividerClockIsStable = 0,
2031 /// Clock frequency is not stable.
2032 ClockFrequencyIsNotStable = 1
2033 ]
2034],
2035ADCCLKDIV [
2036 /// Clock divider value.
2037 DIV OFFSET(0) NUMBITS(3) [],
2038 /// Resets the divider counter.
2039 RESET OFFSET(29) NUMBITS(1) [
2040 /// Divider is not reset.
2041 DividerIsNotReset = 0,
2042 /// Divider is reset.
2043 DividerIsReset = 1
2044 ],
2045 /// Halts the divider counter.
2046 HALT OFFSET(30) NUMBITS(1) [
2047 /// Divider clock is running.
2048 DividerClockIsRunning = 0,
2049 /// Divider clock is stoped.
2050 DividerClockIsStoped = 1
2051 ],
2052 /// Divider status flag.
2053 REQFLAG OFFSET(31) NUMBITS(1) [
2054 /// Divider clock is stable.
2055 DividerClockIsStable = 0,
2056 /// Clock frequency is not stable.
2057 ClockFrequencyIsNotStable = 1
2058 ]
2059],
2060USB0CLKDIV [
2061 /// Clock divider value.
2062 DIV OFFSET(0) NUMBITS(8) [],
2063 /// Resets the divider counter.
2064 RESET OFFSET(29) NUMBITS(1) [
2065 /// Divider is not reset.
2066 DividerIsNotReset = 0,
2067 /// Divider is reset.
2068 DividerIsReset = 1
2069 ],
2070 /// Halts the divider counter.
2071 HALT OFFSET(30) NUMBITS(1) [
2072 /// Divider clock is running.
2073 DividerClockIsRunning = 0,
2074 /// Divider clock is stoped.
2075 DividerClockIsStoped = 1
2076 ],
2077 /// Divider status flag.
2078 REQFLAG OFFSET(31) NUMBITS(1) [
2079 /// Divider clock is stable.
2080 DividerClockIsStable = 0,
2081 /// Clock frequency is not stable.
2082 ClockFrequencyIsNotStable = 1
2083 ]
2084],
2085MCLKDIV [
2086 /// Clock divider value.
2087 DIV OFFSET(0) NUMBITS(8) [],
2088 /// Resets the divider counter.
2089 RESET OFFSET(29) NUMBITS(1) [
2090 /// Divider is not reset.
2091 DividerIsNotReset = 0,
2092 /// Divider is reset.
2093 DividerIsReset = 1
2094 ],
2095 /// Halts the divider counter.
2096 HALT OFFSET(30) NUMBITS(1) [
2097 /// Divider clock is running.
2098 DividerClockIsRunning = 0,
2099 /// Divider clock is stoped.
2100 DividerClockIsStoped = 1
2101 ],
2102 /// Divider status flag.
2103 REQFLAG OFFSET(31) NUMBITS(1) [
2104 /// Divider clock is stable.
2105 DividerClockIsStable = 0,
2106 /// Clock frequency is not stable.
2107 ClockFrequencyIsNotStable = 1
2108 ]
2109],
2110SCTCLKDIV [
2111 /// Clock divider value.
2112 DIV OFFSET(0) NUMBITS(8) [],
2113 /// Resets the divider counter.
2114 RESET OFFSET(29) NUMBITS(1) [
2115 /// Divider is not reset.
2116 DividerIsNotReset = 0,
2117 /// Divider is reset.
2118 DividerIsReset = 1
2119 ],
2120 /// Halts the divider counter.
2121 HALT OFFSET(30) NUMBITS(1) [
2122 /// Divider clock is running.
2123 DividerClockIsRunning = 0,
2124 /// Divider clock is stoped.
2125 DividerClockIsStoped = 1
2126 ],
2127 /// Divider status flag.
2128 REQFLAG OFFSET(31) NUMBITS(1) [
2129 /// Divider clock is stable.
2130 DividerClockIsStable = 0,
2131 /// Clock frequency is not stable.
2132 ClockFrequencyIsNotStable = 1
2133 ]
2134],
2135SDIOCLKDIV [
2136 /// Clock divider value.
2137 DIV OFFSET(0) NUMBITS(8) [],
2138 /// Resets the divider counter.
2139 RESET OFFSET(29) NUMBITS(1) [
2140 /// Divider is not reset.
2141 DividerIsNotReset = 0,
2142 /// Divider is reset.
2143 DividerIsReset = 1
2144 ],
2145 /// Halts the divider counter.
2146 HALT OFFSET(30) NUMBITS(1) [
2147 /// Divider clock is running.
2148 DividerClockIsRunning = 0,
2149 /// Divider clock is stoped.
2150 DividerClockIsStoped = 1
2151 ],
2152 /// Divider status flag.
2153 REQFLAG OFFSET(31) NUMBITS(1) [
2154 /// Divider clock is stable.
2155 DividerClockIsStable = 0,
2156 /// Clock frequency is not stable.
2157 ClockFrequencyIsNotStable = 1
2158 ]
2159],
2160PLL0CLKDIV [
2161 /// Clock divider value.
2162 DIV OFFSET(0) NUMBITS(8) [],
2163 /// Resets the divider counter.
2164 RESET OFFSET(29) NUMBITS(1) [
2165 /// Divider is not reset.
2166 DividerIsNotReset = 0,
2167 /// Divider is reset.
2168 DividerIsReset = 1
2169 ],
2170 /// Halts the divider counter.
2171 HALT OFFSET(30) NUMBITS(1) [
2172 /// Divider clock is running.
2173 DividerClockIsRunning = 0,
2174 /// Divider clock is stoped.
2175 DividerClockIsStoped = 1
2176 ],
2177 /// Divider status flag.
2178 REQFLAG OFFSET(31) NUMBITS(1) [
2179 /// Divider clock is stable.
2180 DividerClockIsStable = 0,
2181 /// Clock frequency is not stable.
2182 ClockFrequencyIsNotStable = 1
2183 ]
2184],
2185CLOCKGENUPDATELOCKOUT [
2186 /// Control clock configuration registers access (like xxxDIV, xxxSEL).
2187 CLOCKGENUPDATELOCKOUT OFFSET(0) NUMBITS(32) [
2188 /// all hardware clock configruration are freeze.
2189 AllHardwareClockConfigrurationAreFreeze = 0,
2190 /// update all clock configuration.
2191 UpdateAllClockConfiguration = 1
2192 ]
2193],
2194FMCCR [
2195 /// Instruction fetch configuration.
2196 FETCHCFG OFFSET(0) NUMBITS(2) [
2197 /// Instruction fetches from flash are not buffered.
2198 InstructionFetchesFromFlashAreNotBuffered = 0,
2199 /// One buffer is used for all instruction fetches.
2200 OneBufferIsUsedForAllInstructionFetches = 1,
2201 /// All buffers may be used for instruction fetches.
2202 AllBuffersMayBeUsedForInstructionFetches = 2
2203 ],
2204 /// Data read configuration.
2205 DATACFG OFFSET(2) NUMBITS(2) [
2206 /// Data accesses from flash are not buffered.
2207 DataAccessesFromFlashAreNotBuffered = 0,
2208 /// One buffer is used for all data accesses.
2209 OneBufferIsUsedForAllDataAccesses = 1,
2210 /// All buffers can be used for data accesses.
2211 AllBuffersCanBeUsedForDataAccesses = 2
2212 ],
2213 /// Acceleration enable.
2214 ACCEL OFFSET(4) NUMBITS(1) [
2215 /// Flash acceleration is disabled.
2216 FlashAccelerationIsDisabled = 0,
2217 /// Flash acceleration is enabled.
2218 FlashAccelerationIsEnabled = 1
2219 ],
2220 /// Prefetch enable.
2221 PREFEN OFFSET(5) NUMBITS(1) [
2222 /// No instruction prefetch is performed.
2223 NoInstructionPrefetchIsPerformed = 0,
2224 /// Instruction prefetch is enabled.
2225 InstructionPrefetchIsEnabled = 1
2226 ],
2227 /// Prefetch override.
2228 PREFOVR OFFSET(6) NUMBITS(1) [
2229 /// Any previously initiated prefetch will be completed.
2230 AnyPreviouslyInitiatedPrefetchWillBeCompleted = 0,
2231 /// Any previously initiated prefetch will be aborted, and the next flash line follo
2232 OVERRIDE = 1
2233 ],
2234 /// Flash memory access time.
2235 FLASHTIM OFFSET(12) NUMBITS(4) [
2236 /// 1 system clock flash access time (for system clock rates up to 11 MHz).
2237 _1SystemClockFlashAccessTimeForSystemClockRatesUpTo11MHz = 0,
2238 /// 2 system clocks flash access time (for system clock rates up to 22 MHz).
2239 _2SystemClocksFlashAccessTimeForSystemClockRatesUpTo22MHz = 1,
2240 /// 3 system clocks flash access time (for system clock rates up to 33 MHz).
2241 _3SystemClocksFlashAccessTimeForSystemClockRatesUpTo33MHz = 2,
2242 /// 4 system clocks flash access time (for system clock rates up to 44 MHz).
2243 _4SystemClocksFlashAccessTimeForSystemClockRatesUpTo44MHz = 3,
2244 /// 5 system clocks flash access time (for system clock rates up to 55 MHz).
2245 _5SystemClocksFlashAccessTimeForSystemClockRatesUpTo55MHz = 4,
2246 /// 6 system clocks flash access time (for system clock rates up to 66 MHz).
2247 _6SystemClocksFlashAccessTimeForSystemClockRatesUpTo66MHz = 5,
2248 /// 7 system clocks flash access time (for system clock rates up to 77 MHz).
2249 _7SystemClocksFlashAccessTimeForSystemClockRatesUpTo77MHz = 6,
2250 /// 8 system clocks flash access time (for system clock rates up to 88 MHz).
2251 _8SystemClocksFlashAccessTimeForSystemClockRatesUpTo88MHz = 7,
2252 /// 9 system clocks flash access time (for system clock rates up to 100 MHz).
2253 _9SystemClocksFlashAccessTimeForSystemClockRatesUpTo100MHz = 8,
2254 /// 10 system clocks flash access time (for system clock rates up to 115 MHz).
2255 _10SystemClocksFlashAccessTimeForSystemClockRatesUpTo115MHz = 9,
2256 /// 11 system clocks flash access time (for system clock rates up to 130 MHz).
2257 _11SystemClocksFlashAccessTimeForSystemClockRatesUpTo130MHz = 10,
2258 /// 12 system clocks flash access time (for system clock rates up to 150 MHz).
2259 _12SystemClocksFlashAccessTimeForSystemClockRatesUpTo150MHz = 11
2260 ]
2261],
2262USB0NEEDCLKCTRL [
2263 /// USB0 Device USB0_NEEDCLK signal control:.
2264 AP_FS_DEV_NEEDCLK OFFSET(0) NUMBITS(1) [
2265 /// Under hardware control.
2266 UnderHardwareControl = 0,
2267 /// Forced high.
2268 ForcedHigh = 1
2269 ],
2270 /// USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.
2271 POL_FS_DEV_NEEDCLK OFFSET(1) NUMBITS(1) [
2272 /// Falling edge of device USB0_NEEDCLK triggers wake-up.
2273 FallingEdgeOfDeviceUSB0_NEEDCLKTriggersWakeUp = 0,
2274 /// Rising edge of device USB0_NEEDCLK triggers wake-up.
2275 RisingEdgeOfDeviceUSB0_NEEDCLKTriggersWakeUp = 1
2276 ],
2277 /// USB0 Host USB0_NEEDCLK signal control:.
2278 AP_FS_HOST_NEEDCLK OFFSET(2) NUMBITS(1) [
2279 /// Under hardware control.
2280 UnderHardwareControl = 0,
2281 /// Forced high.
2282 ForcedHigh = 1
2283 ],
2284 /// USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.
2285 POL_FS_HOST_NEEDCLK OFFSET(3) NUMBITS(1) [
2286 /// Falling edge of device USB0_NEEDCLK triggers wake-up.
2287 FallingEdgeOfDeviceUSB0_NEEDCLKTriggersWakeUp = 0,
2288 /// Rising edge of device USB0_NEEDCLK triggers wake-up.
2289 RisingEdgeOfDeviceUSB0_NEEDCLKTriggersWakeUp = 1
2290 ]
2291],
2292USB0NEEDCLKSTAT [
2293 /// USB0 Device USB0_NEEDCLK signal status:.
2294 DEV_NEEDCLK OFFSET(0) NUMBITS(1) [
2295 /// USB0 Device clock is low.
2296 USB0DeviceClockIsLow = 0,
2297 /// USB0 Device clock is high.
2298 USB0DeviceClockIsHigh = 1
2299 ],
2300 /// USB0 Host USB0_NEEDCLK signal status:.
2301 HOST_NEEDCLK OFFSET(1) NUMBITS(1) [
2302 /// USB0 Host clock is low.
2303 USB0HostClockIsLow = 0,
2304 /// USB0 Host clock is high.
2305 USB0HostClockIsHigh = 1
2306 ]
2307],
2308FMCFLUSH [
2309 /// Flush control
2310 FLUSH OFFSET(0) NUMBITS(1) [
2311 /// No action is performed.
2312 NoActionIsPerformed = 0,
2313 /// Flush the FMC buffer contents.
2314 FlushTheFMCBufferContents = 1
2315 ]
2316],
2317MCLKIO [
2318 /// MCLK control.
2319 MCLKIO OFFSET(0) NUMBITS(1) [
2320 /// input mode.
2321 InputMode = 0,
2322 /// output mode.
2323 OutputMode = 1
2324 ]
2325],
2326USB1NEEDCLKCTRL [
2327 /// USB1 Device need_clock signal control:
2328 AP_HS_DEV_NEEDCLK OFFSET(0) NUMBITS(1) [
2329 /// HOST_NEEDCLK is under hardware control.
2330 HOST_NEEDCLKIsUnderHardwareControl = 0,
2331 /// HOST_NEEDCLK is forced high.
2332 HOST_NEEDCLKIsForcedHigh = 1
2333 ],
2334 /// USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrup
2335 POL_HS_DEV_NEEDCLK OFFSET(1) NUMBITS(1) [
2336 /// Falling edge of DEV_NEEDCLK triggers wake-up.
2337 FallingEdgeOfDEV_NEEDCLKTriggersWakeUp = 0,
2338 /// Rising edge of DEV_NEEDCLK triggers wake-up.
2339 RisingEdgeOfDEV_NEEDCLKTriggersWakeUp = 1
2340 ],
2341 /// USB1 Host need clock signal control:
2342 AP_HS_HOST_NEEDCLK OFFSET(2) NUMBITS(1) [
2343 /// HOST_NEEDCLK is under hardware control.
2344 HOST_NEEDCLKIsUnderHardwareControl = 0,
2345 /// HOST_NEEDCLK is forced high.
2346 HOST_NEEDCLKIsForcedHigh = 1
2347 ],
2348 /// USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt.
2349 POL_HS_HOST_NEEDCLK OFFSET(3) NUMBITS(1) [
2350 /// Falling edge of HOST_NEEDCLK triggers wake-up.
2351 FallingEdgeOfHOST_NEEDCLKTriggersWakeUp = 0,
2352 /// Rising edge of HOST_NEEDCLK triggers wake-up.
2353 RisingEdgeOfHOST_NEEDCLKTriggersWakeUp = 1
2354 ],
2355 /// Software override of device controller PHY wake up logic.
2356 HS_DEV_WAKEUP_N OFFSET(4) NUMBITS(1) [
2357 /// Forces USB1_PHY to wake-up.
2358 ForcesUSB1_PHYToWakeUp = 0,
2359 /// Normal USB1_PHY behavior.
2360 NormalUSB1_PHYBehavior = 1
2361 ]
2362],
2363USB1NEEDCLKSTAT [
2364 /// USB1 Device need_clock signal status:.
2365 DEV_NEEDCLK OFFSET(0) NUMBITS(1) [
2366 /// DEV_NEEDCLK is low.
2367 DEV_NEEDCLKIsLow = 0,
2368 /// DEV_NEEDCLK is high.
2369 DEV_NEEDCLKIsHigh = 1
2370 ],
2371 /// USB1 Host need_clock signal status:.
2372 HOST_NEEDCLK OFFSET(1) NUMBITS(1) [
2373 /// HOST_NEEDCLK is low.
2374 HOST_NEEDCLKIsLow = 0,
2375 /// HOST_NEEDCLK is high.
2376 HOST_NEEDCLKIsHigh = 1
2377 ]
2378],
2379SDIOCLKCTRL [
2380 /// Programmable delay value by which cclk_in_drv is phase-shifted with regard to cc
2381 CCLK_DRV_PHASE OFFSET(0) NUMBITS(2) [
2382 /// 0 degree shift.
2383 _0DegreeShift = 0,
2384 /// 90 degree shift.
2385 _90DegreeShift = 1,
2386 /// 180 degree shift.
2387 _180DegreeShift = 2,
2388 /// 270 degree shift.
2389 _270DegreeShift = 3
2390 ],
2391 /// Programmable delay value by which cclk_in_sample is delayed with regard to cclk_
2392 CCLK_SAMPLE_PHASE OFFSET(2) NUMBITS(2) [
2393 /// 0 degree shift.
2394 _0DegreeShift = 0,
2395 /// 90 degree shift.
2396 _90DegreeShift = 1,
2397 /// 180 degree shift.
2398 _180DegreeShift = 2,
2399 /// 270 degree shift.
2400 _270DegreeShift = 3
2401 ],
2402 /// Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.
2403 PHASE_ACTIVE OFFSET(7) NUMBITS(1) [
2404 /// Bypassed.
2405 Bypassed = 0,
2406 /// Activates phase shift logic. When active, the clock divider is active and phase
2407 PH_SHIFT = 1
2408 ],
2409 /// Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
2410 CCLK_DRV_DELAY OFFSET(16) NUMBITS(5) [],
2411 /// Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
2412 CCLK_DRV_DELAY_ACTIVE OFFSET(23) NUMBITS(1) [
2413 /// Disable drive delay.
2414 DisableDriveDelay = 0,
2415 /// Enable drive delay.
2416 EnableDriveDelay = 1
2417 ],
2418 /// Programmable delay value by which cclk_in_sample is delayed with regard to cclk_
2419 CCLK_SAMPLE_DELAY OFFSET(24) NUMBITS(5) [],
2420 /// Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
2421 CCLK_SAMPLE_DELAY_ACTIVE OFFSET(31) NUMBITS(1) [
2422 /// Disables sample delay.
2423 DisablesSampleDelay = 0,
2424 /// Enables sample delay.
2425 EnablesSampleDelay = 1
2426 ]
2427],
2428PLL1CTRL [
2429 /// Bandwidth select R value.
2430 SELR OFFSET(0) NUMBITS(4) [],
2431 /// Bandwidth select I value.
2432 SELI OFFSET(4) NUMBITS(6) [],
2433 /// Bandwidth select P value.
2434 SELP OFFSET(10) NUMBITS(5) [],
2435 /// Bypass PLL input clock is sent directly to the PLL output (default).
2436 BYPASSPLL OFFSET(15) NUMBITS(1) [
2437 /// use PLL.
2438 UsePLL = 0,
2439 /// PLL input clock is sent directly to the PLL output.
2440 PLLInputClockIsSentDirectlyToThePLLOutput = 1
2441 ],
2442 /// bypass of the divide-by-2 divider in the post-divider.
2443 BYPASSPOSTDIV2 OFFSET(16) NUMBITS(1) [
2444 /// use the divide-by-2 divider in the post-divider.
2445 UseTheDivideBy2DividerInThePostDivider = 0,
2446 /// bypass of the divide-by-2 divider in the post-divider.
2447 BypassOfTheDivideBy2DividerInThePostDivider = 1
2448 ],
2449 /// limup_off = 1 in spread spectrum and fractional PLL applications.
2450 LIMUPOFF OFFSET(17) NUMBITS(1) [],
2451 /// control of the bandwidth of the PLL.
2452 BWDIRECT OFFSET(18) NUMBITS(1) [
2453 /// the bandwidth is changed synchronously with the feedback-divider.
2454 TheBandwidthIsChangedSynchronouslyWithTheFeedbackDivider = 0,
2455 /// modify the bandwidth of the PLL directly.
2456 ModifyTheBandwidthOfThePLLDirectly = 1
2457 ],
2458 /// bypass of the pre-divider.
2459 BYPASSPREDIV OFFSET(19) NUMBITS(1) [
2460 /// use the pre-divider.
2461 UseThePreDivider = 0,
2462 /// bypass of the pre-divider.
2463 BypassOfThePreDivider = 1
2464 ],
2465 /// bypass of the post-divider.
2466 BYPASSPOSTDIV OFFSET(20) NUMBITS(1) [
2467 /// use the post-divider.
2468 UseThePostDivider = 0,
2469 /// bypass of the post-divider.
2470 BypassOfThePostDivider = 1
2471 ],
2472 /// enable the output clock.
2473 CLKEN OFFSET(21) NUMBITS(1) [
2474 /// Disable the output clock.
2475 DisableTheOutputClock = 0,
2476 /// Enable the output clock.
2477 EnableTheOutputClock = 1
2478 ],
2479 /// 1: free running mode.
2480 FRMEN OFFSET(22) NUMBITS(1) [],
2481 /// free running mode clockstable: Warning: Only make frm_clockstable = 1 after the
2482 FRMCLKSTABLE OFFSET(23) NUMBITS(1) [],
2483 /// Skew mode.
2484 SKEWEN OFFSET(24) NUMBITS(1) [
2485 /// skewmode is disable.
2486 SkewmodeIsDisable = 0,
2487 /// skewmode is enable.
2488 SkewmodeIsEnable = 1
2489 ]
2490],
2491PLL1STAT [
2492 /// lock detector output (active high) Warning: The lock signal is only reliable bet
2493 LOCK OFFSET(0) NUMBITS(1) [],
2494 /// pre-divider ratio change acknowledge.
2495 PREDIVACK OFFSET(1) NUMBITS(1) [],
2496 /// feedback divider ratio change acknowledge.
2497 FEEDDIVACK OFFSET(2) NUMBITS(1) [],
2498 /// post-divider ratio change acknowledge.
2499 POSTDIVACK OFFSET(3) NUMBITS(1) [],
2500 /// free running detector output (active high).
2501 FRMDET OFFSET(4) NUMBITS(1) []
2502],
2503PLL1NDEC [
2504 /// pre-divider divider ratio (N-divider).
2505 NDIV OFFSET(0) NUMBITS(8) [],
2506 /// pre-divider ratio change request.
2507 NREQ OFFSET(8) NUMBITS(1) []
2508],
2509PLL1MDEC [
2510 /// feedback divider divider ratio (M-divider).
2511 MDIV OFFSET(0) NUMBITS(16) [],
2512 /// feedback ratio change request.
2513 MREQ OFFSET(16) NUMBITS(1) []
2514],
2515PLL1PDEC [
2516 /// post-divider divider ratio (P-divider)
2517 PDIV OFFSET(0) NUMBITS(5) [],
2518 /// feedback ratio change request.
2519 PREQ OFFSET(5) NUMBITS(1) []
2520],
2521PLL0CTRL [
2522 /// Bandwidth select R value.
2523 SELR OFFSET(0) NUMBITS(4) [],
2524 /// Bandwidth select I value.
2525 SELI OFFSET(4) NUMBITS(6) [],
2526 /// Bandwidth select P value.
2527 SELP OFFSET(10) NUMBITS(5) [],
2528 /// Bypass PLL input clock is sent directly to the PLL output (default).
2529 BYPASSPLL OFFSET(15) NUMBITS(1) [
2530 /// use PLL.
2531 UsePLL = 0,
2532 /// Bypass PLL input clock is sent directly to the PLL output.
2533 BypassPLLInputClockIsSentDirectlyToThePLLOutput = 1
2534 ],
2535 /// bypass of the divide-by-2 divider in the post-divider.
2536 BYPASSPOSTDIV2 OFFSET(16) NUMBITS(1) [
2537 /// use the divide-by-2 divider in the post-divider.
2538 UseTheDivideBy2DividerInThePostDivider = 0,
2539 /// bypass of the divide-by-2 divider in the post-divider.
2540 BypassOfTheDivideBy2DividerInThePostDivider = 1
2541 ],
2542 /// limup_off = 1 in spread spectrum and fractional PLL applications.
2543 LIMUPOFF OFFSET(17) NUMBITS(1) [],
2544 /// Control of the bandwidth of the PLL.
2545 BWDIRECT OFFSET(18) NUMBITS(1) [
2546 /// the bandwidth is changed synchronously with the feedback-divider.
2547 TheBandwidthIsChangedSynchronouslyWithTheFeedbackDivider = 0,
2548 /// modify the bandwidth of the PLL directly.
2549 ModifyTheBandwidthOfThePLLDirectly = 1
2550 ],
2551 /// bypass of the pre-divider.
2552 BYPASSPREDIV OFFSET(19) NUMBITS(1) [
2553 /// use the pre-divider.
2554 UseThePreDivider = 0,
2555 /// bypass of the pre-divider.
2556 BypassOfThePreDivider = 1
2557 ],
2558 /// bypass of the post-divider.
2559 BYPASSPOSTDIV OFFSET(20) NUMBITS(1) [
2560 /// use the post-divider.
2561 UseThePostDivider = 0,
2562 /// bypass of the post-divider.
2563 BypassOfThePostDivider = 1
2564 ],
2565 /// enable the output clock.
2566 CLKEN OFFSET(21) NUMBITS(1) [
2567 /// disable the output clock.
2568 DisableTheOutputClock = 0,
2569 /// enable the output clock.
2570 EnableTheOutputClock = 1
2571 ],
2572 /// free running mode.
2573 FRMEN OFFSET(22) NUMBITS(1) [
2574 /// free running mode is disable.
2575 FreeRunningModeIsDisable = 0,
2576 /// free running mode is enable.
2577 FreeRunningModeIsEnable = 1
2578 ],
2579 /// free running mode clockstable: Warning: Only make frm_clockstable =1 after the P
2580 FRMCLKSTABLE OFFSET(23) NUMBITS(1) [],
2581 /// skew mode.
2582 SKEWEN OFFSET(24) NUMBITS(1) [
2583 /// skew mode is disable.
2584 SkewModeIsDisable = 0,
2585 /// skew mode is enable.
2586 SkewModeIsEnable = 1
2587 ]
2588],
2589PLL0STAT [
2590 /// lock detector output (active high) Warning: The lock signal is only reliable bet
2591 LOCK OFFSET(0) NUMBITS(1) [],
2592 /// pre-divider ratio change acknowledge.
2593 PREDIVACK OFFSET(1) NUMBITS(1) [],
2594 /// feedback divider ratio change acknowledge.
2595 FEEDDIVACK OFFSET(2) NUMBITS(1) [],
2596 /// post-divider ratio change acknowledge.
2597 POSTDIVACK OFFSET(3) NUMBITS(1) [],
2598 /// free running detector output (active high).
2599 FRMDET OFFSET(4) NUMBITS(1) []
2600],
2601PLL0NDEC [
2602 /// pre-divider divider ratio (N-divider).
2603 NDIV OFFSET(0) NUMBITS(8) [],
2604 /// pre-divider ratio change request.
2605 NREQ OFFSET(8) NUMBITS(1) []
2606],
2607PLL0PDEC [
2608 /// post-divider divider ratio (P-divider)
2609 PDIV OFFSET(0) NUMBITS(5) [],
2610 /// feedback ratio change request.
2611 PREQ OFFSET(5) NUMBITS(1) []
2612],
2613PLL0SSCG0 [
2614 /// input word of the wrapper bit 31 to 0.
2615 MD_LBS OFFSET(0) NUMBITS(32) []
2616],
2617PLL0SSCG1 [
2618 /// input word of the wrapper bit 32.
2619 MD_MBS OFFSET(0) NUMBITS(1) [],
2620 /// md change request.
2621 MD_REQ OFFSET(1) NUMBITS(1) [],
2622 /// programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3
2623 MF OFFSET(2) NUMBITS(3) [],
2624 /// programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[3
2625 MR OFFSET(5) NUMBITS(3) [],
2626 /// modulation waveform control Compensation for low pass filtering of the PLL to ge
2627 MC OFFSET(8) NUMBITS(2) [],
2628 /// to select an external mdiv value.
2629 MDIV_EXT OFFSET(10) NUMBITS(16) [],
2630 /// to select an external mreq value.
2631 MREQ OFFSET(26) NUMBITS(1) [],
2632 /// dithering between two modulation frequencies in a random way or in a pseudo rand
2633 DITHER OFFSET(27) NUMBITS(1) [],
2634 /// to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext =
2635 SEL_EXT OFFSET(28) NUMBITS(1) []
2636],
2637FUNCRETENTIONCTRL [
2638 /// functional retention in power down only.
2639 FUNCRETENA OFFSET(0) NUMBITS(1) [
2640 /// disable functional retention.
2641 DisableFunctionalRetention = 0,
2642 /// enable functional retention.
2643 EnableFunctionalRetention = 1
2644 ],
2645 /// Start address divided by 4 inside SRAMX bank.
2646 RET_START OFFSET(1) NUMBITS(13) [],
2647 /// lenth of Scan chains to save.
2648 RET_LENTH OFFSET(14) NUMBITS(10) []
2649],
2650CPUCTRL [
2651 /// CPU1 clock enable.
2652 CPU1CLKEN OFFSET(3) NUMBITS(1) [
2653 /// The CPU1 clock is not enabled.
2654 TheCPU1ClockIsNotEnabled = 0,
2655 /// The CPU1 clock is enabled.
2656 TheCPU1ClockIsEnabled = 1
2657 ],
2658 /// CPU1 reset.
2659 CPU1RSTEN OFFSET(5) NUMBITS(1) [
2660 /// The CPU1 is not being reset.
2661 TheCPU1IsNotBeingReset = 0,
2662 /// The CPU1 is being reset.
2663 TheCPU1IsBeingReset = 1
2664 ]
2665],
2666CPBOOT [
2667 /// Coprocessor Boot Address for CPU1.
2668 CPBOOT OFFSET(0) NUMBITS(32) []
2669],
2670CPSTAT [
2671 /// The CPU0 sleeping state.
2672 CPU0SLEEPING OFFSET(0) NUMBITS(1) [
2673 /// the CPU is not sleeping.
2674 TheCPUIsNotSleeping = 0,
2675 /// the CPU is sleeping.
2676 TheCPUIsSleeping = 1
2677 ],
2678 /// The CPU1 sleeping state.
2679 CPU1SLEEPING OFFSET(1) NUMBITS(1) [
2680 /// the CPU is not sleeping.
2681 TheCPUIsNotSleeping = 0,
2682 /// the CPU is sleeping.
2683 TheCPUIsSleeping = 1
2684 ],
2685 /// The CPU0 lockup state.
2686 CPU0LOCKUP OFFSET(2) NUMBITS(1) [
2687 /// the CPU is not in lockup.
2688 TheCPUIsNotInLockup = 0,
2689 /// the CPU is in lockup.
2690 TheCPUIsInLockup = 1
2691 ],
2692 /// The CPU1 lockup state.
2693 CPU1LOCKUP OFFSET(3) NUMBITS(1) [
2694 /// the CPU is not in lockup.
2695 TheCPUIsNotInLockup = 0,
2696 /// the CPU is in lockup.
2697 TheCPUIsInLockup = 1
2698 ]
2699],
2700CLOCK_CTRL [
2701 /// Enable XTAL32MHz clock for Frequency Measure module.
2702 XTAL32MHZ_FREQM_ENA OFFSET(1) NUMBITS(1) [
2703 /// The clock is not enabled.
2704 TheClockIsNotEnabled = 0,
2705 /// The clock is enabled.
2706 TheClockIsEnabled = 1
2707 ],
2708 /// Enable FRO 1MHz clock for Frequency Measure module and for UTICK.
2709 FRO1MHZ_UTICK_ENA OFFSET(2) NUMBITS(1) [
2710 /// The clock is not enabled.
2711 TheClockIsNotEnabled = 0,
2712 /// The clock is enabled.
2713 TheClockIsEnabled = 1
2714 ],
2715 /// Enable FRO 12MHz clock for Frequency Measure module.
2716 FRO12MHZ_FREQM_ENA OFFSET(3) NUMBITS(1) [
2717 /// The clock is not enabled.
2718 TheClockIsNotEnabled = 0,
2719 /// The clock is enabled.
2720 TheClockIsEnabled = 1
2721 ],
2722 /// Enable FRO 96MHz clock for Frequency Measure module.
2723 FRO_HF_FREQM_ENA OFFSET(4) NUMBITS(1) [
2724 /// The clock is not enabled.
2725 TheClockIsNotEnabled = 0,
2726 /// The clock is enabled.
2727 TheClockIsEnabled = 1
2728 ],
2729 /// Enable clock_in clock for clock module.
2730 CLKIN_ENA OFFSET(5) NUMBITS(1) [
2731 /// The clock is not enabled.
2732 TheClockIsNotEnabled = 0,
2733 /// The clock is enabled.
2734 TheClockIsEnabled = 1
2735 ],
2736 /// Enable FRO 1MHz clock for clock muxing in clock gen.
2737 FRO1MHZ_CLK_ENA OFFSET(6) NUMBITS(1) [
2738 /// The clock is not enabled.
2739 TheClockIsNotEnabled = 0,
2740 /// The clock is enabled.
2741 TheClockIsEnabled = 1
2742 ],
2743 /// Enable FRO 12MHz clock for analog control of the FRO 192MHz.
2744 ANA_FRO12M_CLK_ENA OFFSET(7) NUMBITS(1) [
2745 /// The clock is not enabled.
2746 TheClockIsNotEnabled = 0,
2747 /// The clock is enabled.
2748 TheClockIsEnabled = 1
2749 ],
2750 /// Enable clock for cristal oscilator calibration.
2751 XO_CAL_CLK_ENA OFFSET(8) NUMBITS(1) [
2752 /// The clock is not enabled.
2753 TheClockIsNotEnabled = 0,
2754 /// The clock is enabled.
2755 TheClockIsEnabled = 1
2756 ],
2757 /// Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching.
2758 PLU_DEGLITCH_CLK_ENA OFFSET(9) NUMBITS(1) [
2759 /// The clock is not enabled.
2760 TheClockIsNotEnabled = 0,
2761 /// The clock is enabled.
2762 TheClockIsEnabled = 1
2763 ]
2764],
2765COMP_INT_CTRL [
2766 /// Analog Comparator interrupt enable control:.
2767 INT_ENABLE OFFSET(0) NUMBITS(1) [
2768 /// interrupt disable.
2769 InterruptDisable = 0,
2770 /// interrupt enable.
2771 InterruptEnable = 1
2772 ],
2773 /// Analog Comparator interrupt clear.
2774 INT_CLEAR OFFSET(1) NUMBITS(1) [
2775 /// No effect.
2776 NoEffect = 0,
2777 /// Clear the interrupt. Self-cleared bit.
2778 ClearTheInterruptSelfClearedBit = 1
2779 ],
2780 /// Comparator interrupt type selector:.
2781 INT_CTRL OFFSET(2) NUMBITS(3) [
2782 /// The analog comparator interrupt edge sensitive is disabled.
2783 TheAnalogComparatorInterruptEdgeSensitiveIsDisabled = 0,
2784 /// The analog comparator interrupt level sensitive is disabled.
2785 TheAnalogComparatorInterruptLevelSensitiveIsDisabled = 1,
2786 /// analog comparator interrupt is rising edge sensitive.
2787 AnalogComparatorInterruptIsRisingEdgeSensitive = 2,
2788 /// Analog Comparator interrupt is high level sensitive.
2789 AnalogComparatorInterruptIsHighLevelSensitive = 3,
2790 /// analog comparator interrupt is falling edge sensitive.
2791 AnalogComparatorInterruptIsFallingEdgeSensitive = 4,
2792 /// Analog Comparator interrupt is low level sensitive.
2793 AnalogComparatorInterruptIsLowLevelSensitive = 5,
2794 /// analog comparator interrupt is rising and falling edge sensitive.
2795 AnalogComparatorInterruptIsRisingAndFallingEdgeSensitive = 6
2796 ],
2797 /// Select which Analog comparator output (filtered our un-filtered) is used for int
2798 INT_SOURCE OFFSET(5) NUMBITS(1) [
2799 /// Select Analog Comparator filtered output as input for interrupt detection.
2800 SelectAnalogComparatorFilteredOutputAsInputForInterruptDetection = 0,
2801 /// Select Analog Comparator raw output (unfiltered) as input for interrupt detectio
2802 RAW_INT = 1
2803 ]
2804],
2805COMP_INT_STATUS [
2806 /// Interrupt status BEFORE Interrupt Enable.
2807 STATUS OFFSET(0) NUMBITS(1) [
2808 /// no interrupt pending.
2809 NoInterruptPending = 0,
2810 /// interrupt pending.
2811 InterruptPending = 1
2812 ],
2813 /// Interrupt status AFTER Interrupt Enable.
2814 INT_STATUS OFFSET(1) NUMBITS(1) [
2815 /// no interrupt pending.
2816 NoInterruptPending = 0,
2817 /// interrupt pending.
2818 InterruptPending = 1
2819 ],
2820 /// comparator analog output.
2821 VAL OFFSET(2) NUMBITS(1) [
2822 /// P+ is smaller than P-.
2823 PIsSmallerThanP = 0,
2824 /// P+ is greater than P-.
2825 PIsGreaterThanP = 1
2826 ]
2827],
2828AUTOCLKGATEOVERRIDE [
2829 /// Control automatic clock gating of ROM controller.
2830 ROM OFFSET(0) NUMBITS(1) [
2831 /// Automatic clock gating is not overridden.
2832 AutomaticClockGatingIsNotOverridden = 0,
2833 /// Automatic clock gating is overridden (Clock gating is disabled).
2834 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2835 ],
2836 /// Control automatic clock gating of RAMX controller.
2837 RAMX_CTRL OFFSET(1) NUMBITS(1) [
2838 /// Automatic clock gating is not overridden.
2839 AutomaticClockGatingIsNotOverridden = 0,
2840 /// Automatic clock gating is overridden (Clock gating is disabled).
2841 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2842 ],
2843 /// Control automatic clock gating of RAM0 controller.
2844 RAM0_CTRL OFFSET(2) NUMBITS(1) [
2845 /// Automatic clock gating is not overridden.
2846 AutomaticClockGatingIsNotOverridden = 0,
2847 /// Automatic clock gating is overridden (Clock gating is disabled).
2848 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2849 ],
2850 /// Control automatic clock gating of RAM1 controller.
2851 RAM1_CTRL OFFSET(3) NUMBITS(1) [
2852 /// Automatic clock gating is not overridden.
2853 AutomaticClockGatingIsNotOverridden = 0,
2854 /// Automatic clock gating is overridden (Clock gating is disabled).
2855 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2856 ],
2857 /// Control automatic clock gating of RAM2 controller.
2858 RAM2_CTRL OFFSET(4) NUMBITS(1) [
2859 /// Automatic clock gating is not overridden.
2860 AutomaticClockGatingIsNotOverridden = 0,
2861 /// Automatic clock gating is overridden (Clock gating is disabled).
2862 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2863 ],
2864 /// Control automatic clock gating of RAM3 controller.
2865 RAM3_CTRL OFFSET(5) NUMBITS(1) [
2866 /// Automatic clock gating is not overridden.
2867 AutomaticClockGatingIsNotOverridden = 0,
2868 /// Automatic clock gating is overridden (Clock gating is disabled).
2869 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2870 ],
2871 /// Control automatic clock gating of RAM4 controller.
2872 RAM4_CTRL OFFSET(6) NUMBITS(1) [
2873 /// Automatic clock gating is not overridden.
2874 AutomaticClockGatingIsNotOverridden = 0,
2875 /// Automatic clock gating is overridden (Clock gating is disabled).
2876 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2877 ],
2878 /// Control automatic clock gating of synchronous bridge controller 0.
2879 SYNC0_APB OFFSET(7) NUMBITS(1) [
2880 /// Automatic clock gating is not overridden.
2881 AutomaticClockGatingIsNotOverridden = 0,
2882 /// Automatic clock gating is overridden (Clock gating is disabled).
2883 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2884 ],
2885 /// Control automatic clock gating of synchronous bridge controller 1.
2886 SYNC1_APB OFFSET(8) NUMBITS(1) [
2887 /// Automatic clock gating is not overridden.
2888 AutomaticClockGatingIsNotOverridden = 0,
2889 /// Automatic clock gating is overridden (Clock gating is disabled).
2890 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2891 ],
2892 /// Control automatic clock gating of CRCGEN controller.
2893 CRCGEN OFFSET(11) NUMBITS(1) [
2894 /// Automatic clock gating is not overridden.
2895 AutomaticClockGatingIsNotOverridden = 0,
2896 /// Automatic clock gating is overridden (Clock gating is disabled).
2897 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2898 ],
2899 /// Control automatic clock gating of DMA0 controller.
2900 SDMA0 OFFSET(12) NUMBITS(1) [
2901 /// Automatic clock gating is not overridden.
2902 AutomaticClockGatingIsNotOverridden = 0,
2903 /// Automatic clock gating is overridden (Clock gating is disabled).
2904 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2905 ],
2906 /// Control automatic clock gating of DMA1 controller.
2907 SDMA1 OFFSET(13) NUMBITS(1) [
2908 /// Automatic clock gating is not overridden.
2909 AutomaticClockGatingIsNotOverridden = 0,
2910 /// Automatic clock gating is overridden (Clock gating is disabled).
2911 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2912 ],
2913 /// Control automatic clock gating of USB controller.
2914 USB0 OFFSET(14) NUMBITS(1) [
2915 /// Automatic clock gating is not overridden.
2916 AutomaticClockGatingIsNotOverridden = 0,
2917 /// Automatic clock gating is overridden (Clock gating is disabled).
2918 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2919 ],
2920 /// Control automatic clock gating of synchronous system controller registers bank.
2921 SYSCON OFFSET(15) NUMBITS(1) [
2922 /// Automatic clock gating is not overridden.
2923 AutomaticClockGatingIsNotOverridden = 0,
2924 /// Automatic clock gating is overridden (Clock gating is disabled).
2925 AutomaticClockGatingIsOverriddenClockGatingIsDisabled = 1
2926 ],
2927 /// The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields update
2928 ENABLEUPDATE OFFSET(16) NUMBITS(16) [
2929 /// Bit Fields 0 - 15 of this register are not updated
2930 BitFields015OfThisRegisterAreNotUpdated = 0,
2931 /// Bit Fields 0 - 15 of this register are updated
2932 BitFields015OfThisRegisterAreUpdated = 49374
2933 ]
2934],
2935GPIOPSYNC [
2936 /// Enable bypass of the first stage of synchonization inside GPIO_INT module.
2937 PSYNC OFFSET(0) NUMBITS(1) [
2938 /// use the first stage of synchonization inside GPIO_INT module.
2939 UseTheFirstStageOfSynchonizationInsideGPIO_INTModule = 0,
2940 /// bypass of the first stage of synchonization inside GPIO_INT module.
2941 BypassOfTheFirstStageOfSynchonizationInsideGPIO_INTModule = 1
2942 ]
2943],
2944DEBUG_LOCK_EN [
2945 /// Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITY
2946 LOCK_ALL OFFSET(0) NUMBITS(4) [
2947 /// Any other value than b1010: disable write access to all 6 registers.
2948 AnyOtherValueThanB1010DisableWriteAccessToAll6Registers = 0,
2949 /// 1010: Enable write access to all 6 registers.
2950 _1010EnableWriteAccessToAll6Registers = 10
2951 ]
2952],
2953DEBUG_FEATURES [
2954 /// CPU0 Invasive debug control:.
2955 CPU0_DBGEN OFFSET(0) NUMBITS(2) [
2956 /// Any other value than b10: invasive debug is disable.
2957 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
2958 /// 10: Invasive debug is enabled.
2959 _10InvasiveDebugIsEnabled = 2
2960 ],
2961 /// CPU0 Non Invasive debug control:.
2962 CPU0_NIDEN OFFSET(2) NUMBITS(2) [
2963 /// Any other value than b10: invasive debug is disable.
2964 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
2965 /// 10: Invasive debug is enabled.
2966 _10InvasiveDebugIsEnabled = 2
2967 ],
2968 /// CPU0 Secure Invasive debug control:.
2969 CPU0_SPIDEN OFFSET(4) NUMBITS(2) [
2970 /// Any other value than b10: invasive debug is disable.
2971 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
2972 /// 10: Invasive debug is enabled.
2973 _10InvasiveDebugIsEnabled = 2
2974 ],
2975 /// CPU0 Secure Non Invasive debug control:.
2976 CPU0_SPNIDEN OFFSET(6) NUMBITS(2) [
2977 /// Any other value than b10: invasive debug is disable.
2978 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
2979 /// 10: Invasive debug is enabled.
2980 _10InvasiveDebugIsEnabled = 2
2981 ],
2982 /// CPU1 Invasive debug control:.
2983 CPU1_DBGEN OFFSET(8) NUMBITS(2) [
2984 /// Any other value than b10: invasive debug is disable.
2985 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
2986 /// 10: Invasive debug is enabled.
2987 _10InvasiveDebugIsEnabled = 2
2988 ],
2989 /// CPU1 Non Invasive debug control:.
2990 CPU1_NIDEN OFFSET(10) NUMBITS(2) [
2991 /// Any other value than b10: invasive debug is disable.
2992 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
2993 /// 10: Invasive debug is enabled.
2994 _10InvasiveDebugIsEnabled = 2
2995 ]
2996],
2997DEBUG_FEATURES_DP [
2998 /// CPU0 (CPU0) Invasive debug control:.
2999 CPU0_DBGEN OFFSET(0) NUMBITS(2) [
3000 /// Any other value than b10: invasive debug is disable.
3001 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
3002 /// 10: Invasive debug is enabled.
3003 _10InvasiveDebugIsEnabled = 2
3004 ],
3005 /// CPU0 Non Invasive debug control:.
3006 CPU0_NIDEN OFFSET(2) NUMBITS(2) [
3007 /// Any other value than b10: invasive debug is disable.
3008 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
3009 /// 10: Invasive debug is enabled.
3010 _10InvasiveDebugIsEnabled = 2
3011 ],
3012 /// CPU0 Secure Invasive debug control:.
3013 CPU0_SPIDEN OFFSET(4) NUMBITS(2) [
3014 /// Any other value than b10: invasive debug is disable.
3015 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
3016 /// 10: Invasive debug is enabled.
3017 _10InvasiveDebugIsEnabled = 2
3018 ],
3019 /// CPU0 Secure Non Invasive debug control:.
3020 CPU0_SPNIDEN OFFSET(6) NUMBITS(2) [
3021 /// Any other value than b10: invasive debug is disable.
3022 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
3023 /// 10: Invasive debug is enabled.
3024 _10InvasiveDebugIsEnabled = 2
3025 ],
3026 /// CPU1 Invasive debug control:.
3027 CPU1_DBGEN OFFSET(8) NUMBITS(2) [
3028 /// Any other value than b10: invasive debug is disable.
3029 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
3030 /// 10: Invasive debug is enabled.
3031 _10InvasiveDebugIsEnabled = 2
3032 ],
3033 /// CPU1 Non Invasive debug control:.
3034 CPU1_NIDEN OFFSET(10) NUMBITS(2) [
3035 /// Any other value than b10: invasive debug is disable.
3036 AnyOtherValueThanB10InvasiveDebugIsDisable = 1,
3037 /// 10: Invasive debug is enabled.
3038 _10InvasiveDebugIsEnabled = 2
3039 ]
3040],
3041KEY_BLOCK [
3042 /// Write a value to block quiddikey/PUF all index.
3043 KEY_BLOCK OFFSET(0) NUMBITS(32) []
3044],
3045DEBUG_AUTH_BEACON [
3046 /// Set by the debug authentication code in ROM to pass the debug beacons (Credentia
3047 BEACON OFFSET(0) NUMBITS(32) []
3048],
3049CPUCFG [
3050 /// Enable CPU1.
3051 CPU1ENABLE OFFSET(2) NUMBITS(1) [
3052 /// CPU1 is disable (Processor in reset).
3053 CPU1IsDisableProcessorInReset = 0,
3054 /// CPU1 is enable.
3055 CPU1IsEnable = 1
3056 ]
3057],
3058DEVICE_ID0 [
3059 /// ROM revision.
3060 ROM_REV_MINOR OFFSET(20) NUMBITS(4) []
3061],
3062DIEID [
3063 /// Chip Metal Revision ID.
3064 REV_ID OFFSET(0) NUMBITS(4) [],
3065 /// Chip Number 0x426B.
3066 MCO_NUM_IN_DIE_ID OFFSET(4) NUMBITS(20) []
3067],
3068PRESETCTRLSET0 [
3069 /// Data array value
3070 DATA OFFSET(0) NUMBITS(32) []
3071],
3072PRESETCTRLSET1 [
3073 /// Data array value
3074 DATA OFFSET(0) NUMBITS(32) []
3075],
3076PRESETCTRLSET2 [
3077 /// Data array value
3078 DATA OFFSET(0) NUMBITS(32) []
3079],
3080PRESETCTRLCLR0 [
3081 /// Data array value
3082 DATA OFFSET(0) NUMBITS(32) []
3083],
3084PRESETCTRLCLR1 [
3085 /// Data array value
3086 DATA OFFSET(0) NUMBITS(32) []
3087],
3088PRESETCTRLCLR2 [
3089 /// Data array value
3090 DATA OFFSET(0) NUMBITS(32) []
3091],
3092pub AHBCLKCTRLSET0 [
3093 /// Data array value
3094 DATA OFFSET(0) NUMBITS(32) []
3095],
3096AHBCLKCTRLSET1 [
3097 /// Data array value
3098 DATA OFFSET(0) NUMBITS(32) []
3099],
3100AHBCLKCTRLSET2 [
3101 /// Data array value
3102 DATA OFFSET(0) NUMBITS(32) []
3103],
3104AHBCLKCTRLCLR0 [
3105 /// Data array value
3106 DATA OFFSET(0) NUMBITS(32) []
3107],
3108AHBCLKCTRLCLR1 [
3109 /// Data array value
3110 DATA OFFSET(0) NUMBITS(32) []
3111],
3112AHBCLKCTRLCLR2 [
3113 /// Data array value
3114 DATA OFFSET(0) NUMBITS(32) []
3115]
3116];
3117pub const SYSCON_BASE: StaticRef<SysconRegisters> =
3118 unsafe { StaticRef::new(0x40000000 as *const SysconRegisters) };