litex_arty/
litex_generated_constants.rs1#![allow(unused)]
6
7pub type SoCRegisterFmt = litex_vexriscv::litex_registers::LiteXSoCRegistersC32B32;
9
10pub const UART_BAUDRATE: u32 = 1_000_000;
12
13pub type ClockFrequency = kernel::hil::time::Freq100MHz;
16
17pub const CONFIG_CPU_HAS_INTERRUPT: bool = true;
18pub const CONFIG_CPU_RESET_ADDR: usize = 0;
19
20pub const CONFIG_CPU_TYPE: &str = "vexriscv";
21pub const CONFIG_CPU_VARIANT: &str = "tock";
22pub const CONFIG_CPU_HUMAN_NAME: &str = "VexRiscv_TockSecureIMC";
23pub const CONFIG_CPU_NOP: &str = "nop";
24pub const CONFIG_L2_SIZE: usize = 8192;
25
26pub const CONFIG_CSR_DATA_WIDTH: usize = 32;
27pub const CONFIG_CSR_ALIGNMENT: usize = 32;
28pub const CONFIG_BUS_STANDARD: &str = "WISHBONE";
29pub const CONFIG_BUS_DATA_WIDTH: usize = 32;
30pub const CONFIG_BUS_ADDRESS_WIDTH: usize = 32;
31
32pub const ETHMAC_RX_SLOTS: usize = 2;
33pub const ETHMAC_TX_SLOTS: usize = 2;
34pub const ETHMAC_SLOT_SIZE: usize = 2048;
35
36pub const ETHMAC_INTERRUPT: usize = 2;
37pub const TIMER0_INTERRUPT: usize = 1;
38pub const UART_INTERRUPT: usize = 0;
39
40pub const CSR_BASE: usize = 0xf0000000;
43pub const CSR_BUTTONS_BASE: usize = CSR_BASE + 0x0000;
44pub const CSR_CTRL_BASE: usize = CSR_BASE + 0x0800;
45pub const CSR_DDRPHY_BASE: usize = CSR_BASE + 0x1000;
46pub const CSR_DNA_BASE: usize = CSR_BASE + 0x1800;
47pub const CSR_ETHMAC_BASE: usize = CSR_BASE + 0x2000;
48pub const CSR_ETHPHY_BASE: usize = CSR_BASE + 0x2800;
49pub const CSR_IDENTIFIER_MEM_BASE: usize = CSR_BASE + 0x3000;
50pub const CSR_LEDS_BASE: usize = CSR_BASE + 0x3800;
51pub const CSR_SDRAM_BASE: usize = CSR_BASE + 0x4000;
52pub const CSR_SPIFLASH_CORE_BASE: usize = CSR_BASE + 0x4800;
53pub const CSR_TIMER0_BASE: usize = CSR_BASE + 0x5000;
54pub const CSR_UART_BASE: usize = CSR_BASE + 0x5800;
55pub const CSR_XADC_BASE: usize = CSR_BASE + 0x6000;
56
57pub const MEM_ETHMAC_BASE: usize = 0x80000000;
59pub const MEM_ETHMAC_SIZE: usize = 0x00002000;