imxrt10xx/
iomuxc.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5use enum_primitive::cast::FromPrimitive;
6use enum_primitive::enum_from_primitive;
7use kernel::utilities::registers::interfaces::{ReadWriteable, Readable};
8use kernel::utilities::registers::{register_bitfields, ReadWrite};
9use kernel::utilities::StaticRef;
10
11/// IOMUX Controller Module
12#[repr(C)]
13struct IomuxcRegisters {
14    sw_mux_ctl_pad_gpio_emc: [ReadWrite<u32, SW_MUX_CTL_PAD_GPIO::Register>; 42],
15    sw_mux_ctl_pad_gpio_ad_b0: [ReadWrite<u32, SW_MUX_CTL_PAD_GPIO::Register>; 16],
16    sw_mux_ctl_pad_gpio_ad_b1: [ReadWrite<u32, SW_MUX_CTL_PAD_GPIO::Register>; 16],
17    sw_mux_ctl_pad_gpio_b0: [ReadWrite<u32, SW_MUX_CTL_PAD_GPIO::Register>; 16],
18    sw_mux_ctl_pad_gpio_b1: [ReadWrite<u32, SW_MUX_CTL_PAD_GPIO::Register>; 16],
19    sw_mux_ctl_pad_gpio_sd_b0: [ReadWrite<u32, SW_MUX_CTL_PAD_GPIO::Register>; 6],
20    sw_mux_ctl_pad_gpio_sd_b1: [ReadWrite<u32, SW_MUX_CTL_PAD_GPIO::Register>; 12],
21
22    sw_pad_ctl_pad_gpio_emc: [ReadWrite<u32, SW_PAD_CTL_PAD_GPIO::Register>; 42],
23    sw_pad_ctl_pad_gpio_ad_b0: [ReadWrite<u32, SW_PAD_CTL_PAD_GPIO::Register>; 16],
24    sw_pad_ctl_pad_gpio_ad_b1: [ReadWrite<u32, SW_PAD_CTL_PAD_GPIO::Register>; 16],
25    sw_pad_ctl_pad_gpio_b0: [ReadWrite<u32, SW_PAD_CTL_PAD_GPIO::Register>; 16],
26    sw_pad_ctl_pad_gpio_b1: [ReadWrite<u32, SW_PAD_CTL_PAD_GPIO::Register>; 16],
27    sw_pad_ctl_pad_gpio_sd_b0: [ReadWrite<u32, SW_PAD_CTL_PAD_GPIO::Register>; 6],
28    sw_pad_ctl_pad_gpio_sd_b1: [ReadWrite<u32, SW_PAD_CTL_PAD_GPIO::Register>; 12],
29
30    anatop_usb_otg1_id_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
31    anatop_usb_otg2_id_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
32
33    ccm_pmic_ready_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
34
35    csi_data0_x_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 8],
36    csi_hsync_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
37    csi_pixclk_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
38    csi_vsync_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
39
40    enet_ipg_clk_rmii_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
41    enet_mdio_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
42    enet0_rxdata_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
43    enet1_rxdata_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
44    enet_rxen_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
45    enet_rxerr_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
46    enet0_timer_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
47    enet_txclk_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
48
49    flexcan1_rx_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
50    flexcan2_rx_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
51
52    flexpwm1_pwma3_select_input: ReadWrite<u32, DAISY_3BIT_SELECT_INPUT::Register>,
53    flexpwm1_pwma0_2_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 3],
54    flexpwm1_pwmb3_select_input: ReadWrite<u32, DAISY_3BIT_SELECT_INPUT::Register>,
55    flexpwm1_pwmb0_2_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 3],
56
57    flexpwm2_pwma3_select_input: ReadWrite<u32, DAISY_3BIT_SELECT_INPUT::Register>,
58    flexpwm2_pwma0_2_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 3],
59    flexpwm2_pwmb3_select_input: ReadWrite<u32, DAISY_3BIT_SELECT_INPUT::Register>,
60    flexpwm2_pwmb0_2_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 3],
61
62    flexpwm4_pwma0_3_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 4],
63
64    flexspi_a_dqs_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
65    flexspi_a_data_x_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 4],
66    flexspi_b_data_x_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 4],
67    flexspi_a_sck_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
68
69    lpi2c1_scl_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
70    lpi2c1_sda_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
71
72    lpi2c2_scl_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
73    lpi2c2_sda_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
74
75    lpi2c3_scl_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
76    lpi2c3_sda_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
77
78    lpi2c4_scl_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
79    lpi2c4_sda_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
80
81    lpspi1_pcs0_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
82    lpspi1_sck_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
83    lpspi1_sdi_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
84    lpspi1_sdo_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
85
86    lpspi2_pcs0_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
87    lpspi2_sck_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
88    lpspi2_sdi_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
89    lpspi2_sdo_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
90
91    lpspi3_pcs0_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
92    lpspi3_sck_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
93    lpspi3_sdi_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
94    lpspi3_sdo_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
95
96    lpspi4_pcs0_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
97    lpspi4_sck_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
98    lpspi4_sdi_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
99    lpspi4_sdo_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
100
101    lpuart2_rx_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
102    lpuart2_tx_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
103
104    lpuart3_cts_b_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
105    lpuart3_rx_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
106    lpuart3_tx_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
107
108    lpuart4_rx_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
109    lpuart4_tx_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
110
111    lpuart5_rx_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
112    lpuart5_tx_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
113
114    lpuart6_rx_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
115    lpuart6_tx_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
116
117    lpuart7_rx_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
118    lpuart7_tx_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
119
120    lpuart8_rx_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
121    lpuart8_tx_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
122
123    nmi_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
124
125    qtimer2_timer_x_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 4],
126    qtimer3_timer_x_select_input: [ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>; 4],
127
128    sai1_mclk2_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
129    sai1_rx_bclk_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
130    sai1_rx_data0_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
131    sai1_rx_data1_3_select_input: [ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>; 3],
132    sai1_rx_sync_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
133    sai1_tx_bclk_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
134    sai1_tx_sync_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
135
136    sai2_mclk2_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
137    sai2_rx_bclk_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
138    sai2_rx_data0_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
139    sai2_rx_sync_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
140    sai2_tx_bclk_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
141    sai2_tx_sync_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
142
143    spdif_in_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
144
145    usb_otg2_oc_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
146    usb_otg1_oc_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
147
148    usdhc1_cd_b_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
149    usdhc1_wp_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
150    usdhc2_clk_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
151    usdhc2_cd_b_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
152    usdhc2_cmd_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
153    usdhc2_data_x_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 8],
154    usdhc2_wp_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
155
156    xbar_inout02_09_select_input: [ReadWrite<u32, DAISY_SELECT_INPUT::Register>; 8],
157    xbar_inout17_select_input: ReadWrite<u32, DAISY_2BIT_SELECT_INPUT::Register>,
158    xbar_inout18_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
159    xbar_inout20_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
160    xbar_inout22_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
161    xbar_inout23_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
162    xbar_inout24_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
163    xbar_inout14_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
164    xbar_inout15_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
165    xbar_inout16_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
166    xbar_inout25_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
167    xbar_inout19_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
168    xbar_inout21_select_input: ReadWrite<u32, DAISY_SELECT_INPUT::Register>,
169}
170
171register_bitfields![u32,
172    SW_MUX_CTL_PAD_GPIO [
173        // Software Input On Field
174        SION OFFSET(4) NUMBITS(1) [],
175        // MUX Mode Select Field
176        MUX_MODE OFFSET(0) NUMBITS(3) []
177    ],
178
179    SW_PAD_CTL_PAD_GPIO [
180        // Hyst. Enable Field
181        HYS OFFSET(16) NUMBITS(1) [],
182        // Pull Up / Down Config Field
183        PUS OFFSET(14) NUMBITS(2) [],
184        // Pull / Keep Select Field
185        PUE OFFSET(13) NUMBITS(1) [],
186        // Pull / Keep enable field
187        PKE OFFSET(12) NUMBITS(1) [],
188        // Open drain enable field
189        ODE OFFSET(11) NUMBITS(1) [],
190        // Speed
191        SPEED OFFSET(6) NUMBITS(2) [],
192        // Drive Strength Field
193        DSE OFFSET(3) NUMBITS(3) [],
194        // Slew Rate Field
195        SRE OFFSET(0) NUMBITS(1) []
196    ],
197
198    DAISY_SELECT_INPUT [
199        // Selecting Pads Involved in Daisy Chain.
200        DAISY OFFSET(0) NUMBITS(1) []
201    ],
202
203    DAISY_2BIT_SELECT_INPUT [
204        // Selecting Pads Involved in Daisy Chain.
205        DAISY OFFSET(0) NUMBITS(2) []
206    ],
207
208    DAISY_3BIT_SELECT_INPUT [
209        // Selecting Pads Involved in Daisy Chain.
210        DAISY OFFSET(0) NUMBITS(3) []
211    ]
212];
213
214const IOMUXC_BASE: StaticRef<IomuxcRegisters> =
215    unsafe { StaticRef::new(0x401F8014 as *const IomuxcRegisters) };
216
217pub struct Iomuxc {
218    registers: StaticRef<IomuxcRegisters>,
219}
220
221/// Most of the gpio pins are grouped in the following 7 pads
222///
223/// To control the SNVS pads, use [`IomuxcSnvs`](crate::iomuxc_snvs::IomuxcSnvs).
224#[repr(u32)]
225pub enum PadId {
226    EMC = 0b000,
227    AdB0 = 0b001,
228    AdB1 = 0b010,
229    B0 = 0b011,
230    B1 = 0b100,
231    SdB0 = 0b101,
232    SdB1 = 0b110,
233}
234
235// Sion - Software Input On Field [^1], forces input path of pad, or lets
236// the functionality be determined by the MuxMode [^2]
237//
238// [^1]: Sion functioning: 11.3.2 SW Loopback through SION bit, page 307 of the Reference Manual
239// [^2]: Register values explanation: 11.7.1 SW_MUX_CTL_PAD_GPIO_EMC_00, page 401 of the RM
240#[repr(u32)]
241pub enum Sion {
242    Enabled = 1,
243    Disabled = 0,
244}
245
246// Alternative Modes for Mux Mode Select Field [^1]
247// Each mode is specific for the iomux pad [^2]
248//
249// [^1]: Mux Modes explained: 11.3 Functional description, page 306 of the RM
250// [^2]: Register values explanation: 11.7.1 SW_MUX_CTL_PAD_GPIO_EMC_00, page 401 of the RM
251enum_from_primitive! {
252    #[repr(u32)]
253    pub enum MuxMode {
254       ALT0 = 0b000, // Tipically used for semc, jtag_mux
255       ALT1 = 0b001, // Tipically used for gpt, lpi2c, flexpwm
256       ALT2 = 0b010, // Tipically used for lpuart, lpspi, flexpwm
257       ALT3 = 0b011, // Tipically used for xbar, usdhc
258       ALT4 = 0b100, // Tipically used for flexio, qtimer, gpt
259       ALT5 = 0b101, // Tipically used for gpio mode
260       ALT6 = 0b110, // Rarely used. In EMC_18, used for snvs_hp
261       ALT7 = 0b111, // Rarely used.
262    }
263}
264
265// Hysteresis toggle [^1]
266//
267// [^1]: 12.4.2.1.1 Schmitt trigger, page 1002 of the RM
268#[repr(u32)]
269pub enum HystEn {
270    Hys0HysteresisDisabled = 0b0, //  Hysteresis Disabled (CMOS input)
271    Hys1HysteresisEnabled = 0b1,  //  Hysteresis Enabled (Schmitt Trigger input)
272}
273
274// GPIO pin internal pull-up and pull-down [^1]
275//
276// [^1]: 12.4.2.2 Output Driver, page 1004 of the RM
277#[repr(u32)]
278pub enum PullUpDown {
279    Pus0_100kOhmPullDown = 0b00, //  100K Ohm Pull Down
280    Pus1_47kOhmPullUp = 0b01,    //  47K Ohm Pull Up
281    Pus2_100kOhmPullUp = 0b10,   //  100K Ohm Pull Up
282    Pus3_22kOhmPullUp = 0b11,    //  22K Ohm Pull Up
283}
284
285// Enable or disable latch to hold the value
286//
287// [^1]: Figure 12-7. Keeper functional diagram, page 1005 of the RM
288#[repr(u32)]
289pub enum PullKeepSel {
290    Pue0Keeper = 0b0, // Keep the previous output value when the output driver is disabled
291    Pue1Pull = 0b1,   // Pull-up or pull-down (determined by PUS field).
292}
293
294// Enable dependency of the output on the Keeper. [^1]
295//
296// [^1]: 12.4.2.2.3 PU / PD / Keeper Logic, page 1005 of the RM
297#[repr(u32)]
298pub enum PullKeepEn {
299    Pke0PullKeeperDisabled = 0b0, // Pull/Keeper Disabled
300    Pke1PullKeeperEnabled = 0b1,  // Pull/Keeper Enabled
301}
302
303// Enable bidirectional communication over the same wire [^1]
304//
305// [^1]: 12.4.2.2.4 Open drain, page 1005 of the RM
306#[repr(u32)]
307pub enum OpenDrainEn {
308    Ode0OpenDrainDisabled = 0b0, // Open Drain Disabled (Output is CMOS)
309    Ode1OpenDrainEnabled = 0b1,  // Open Drain Enabled (Output is Open Drain)
310}
311
312// Setting the electrical characteristics of a pin to a specific
313// frequency range. [^1]
314//
315// [^1]: Field description: 11.7.125 IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, page 588 of the RM
316#[repr(u32)]
317pub enum Speed {
318    Low = 0b00,     // 50MHz
319    Medium1 = 0b01, // 100MHz - 150MHz
320    Medium2 = 0b10, // 100MHz - 150MHz
321    Maximum = 0b11, // 150MHz - 200MHz
322}
323
324// Select Drive strength in order to make the impedance matched
325// and get better signal integrity. [^1]
326//
327// [^1]: 12.4.2.2.1 Drive strength, page 1004 of the RM
328#[repr(u32)]
329pub enum DriveStrength {
330    DSE0 = 0b000, // HI-Z
331    DSE1 = 0b001, // Dual/Single voltage: 262/260 Ohm @ 1.8V, 247/157 Ohm @ 3.3V
332    DSE2 = 0b010, // Dual/Single voltage: 134/130 Ohm @ 1.8V, 126/78 Ohm @ 3.3V
333    DSE3 = 0b011, // Dual/Single voltage: 88/88 Ohm @ 1.8V, 84/53 Ohm @ 3.3V
334    DSE4 = 0b100, // Dual/Single voltage: 62/65 Ohm @ 1.8V, 57/39 Ohm @ 3.3V
335    DSE5 = 0b101, // Dual/Single voltage: 51/52 Ohm @ 1.8V, 47/32 Ohm @ 3.3V
336    DSE6 = 0b110, // Dual/Single voltage: 43/43 Ohm @ 1.8V, 40/26 Ohm @ 3.3V
337    DSE7 = 0b111, // Dual/Single voltage: 37/37 Ohm @ 1.8V, 34/23 Ohm @ 3.3V
338}
339
340// How fast a pin toggles between two logic states [^1]
341//
342// [^1]: Field description: 11.7.125 IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, page 589 of the RM
343#[repr(u32)]
344pub enum SlewRate {
345    Sre0SlowSlewRate = 0b0, // Slow Slew Rate
346    Sre1FastSlewRate = 0b1, // Fast Slew Rate
347}
348
349impl Iomuxc {
350    pub const fn new() -> Iomuxc {
351        Iomuxc {
352            registers: IOMUXC_BASE,
353        }
354    }
355
356    pub fn is_enabled_sw_mux_ctl_pad_gpio_mode(&self, pad: PadId, pin: usize) -> bool {
357        match pad {
358            PadId::EMC => {
359                self.registers.sw_mux_ctl_pad_gpio_emc[pin].is_set(SW_MUX_CTL_PAD_GPIO::MUX_MODE)
360            }
361            PadId::AdB0 => {
362                self.registers.sw_mux_ctl_pad_gpio_ad_b0[pin].is_set(SW_MUX_CTL_PAD_GPIO::MUX_MODE)
363            }
364            PadId::AdB1 => {
365                self.registers.sw_mux_ctl_pad_gpio_ad_b1[pin].is_set(SW_MUX_CTL_PAD_GPIO::MUX_MODE)
366            }
367            PadId::B0 => {
368                self.registers.sw_mux_ctl_pad_gpio_b0[pin].is_set(SW_MUX_CTL_PAD_GPIO::MUX_MODE)
369            }
370            PadId::B1 => {
371                self.registers.sw_mux_ctl_pad_gpio_b1[pin].is_set(SW_MUX_CTL_PAD_GPIO::MUX_MODE)
372            }
373            PadId::SdB0 => {
374                self.registers.sw_mux_ctl_pad_gpio_sd_b0[pin].is_set(SW_MUX_CTL_PAD_GPIO::MUX_MODE)
375            }
376            PadId::SdB1 => {
377                self.registers.sw_mux_ctl_pad_gpio_sd_b1[pin].is_set(SW_MUX_CTL_PAD_GPIO::MUX_MODE)
378            }
379        }
380    }
381
382    // Set the functionality mode for a specific pad
383    pub fn enable_sw_mux_ctl_pad_gpio(&self, pad: PadId, mode: MuxMode, sion: Sion, pin: usize) {
384        match pad {
385            PadId::EMC => {
386                self.registers.sw_mux_ctl_pad_gpio_emc[pin].modify(
387                    SW_MUX_CTL_PAD_GPIO::MUX_MODE.val(mode as u32)
388                        + SW_MUX_CTL_PAD_GPIO::SION.val(sion as u32),
389                );
390            }
391            PadId::AdB0 => {
392                self.registers.sw_mux_ctl_pad_gpio_ad_b0[pin].modify(
393                    SW_MUX_CTL_PAD_GPIO::MUX_MODE.val(mode as u32)
394                        + SW_MUX_CTL_PAD_GPIO::SION.val(sion as u32),
395                );
396            }
397            PadId::AdB1 => {
398                self.registers.sw_mux_ctl_pad_gpio_ad_b1[pin].modify(
399                    SW_MUX_CTL_PAD_GPIO::MUX_MODE.val(mode as u32)
400                        + SW_MUX_CTL_PAD_GPIO::SION.val(sion as u32),
401                );
402            }
403            PadId::B0 => {
404                self.registers.sw_mux_ctl_pad_gpio_b0[pin].modify(
405                    SW_MUX_CTL_PAD_GPIO::MUX_MODE.val(mode as u32)
406                        + SW_MUX_CTL_PAD_GPIO::SION.val(sion as u32),
407                );
408            }
409            PadId::B1 => {
410                self.registers.sw_mux_ctl_pad_gpio_b1[pin].modify(
411                    SW_MUX_CTL_PAD_GPIO::MUX_MODE.val(mode as u32)
412                        + SW_MUX_CTL_PAD_GPIO::SION.val(sion as u32),
413                );
414            }
415            PadId::SdB0 => {
416                self.registers.sw_mux_ctl_pad_gpio_sd_b0[pin].modify(
417                    SW_MUX_CTL_PAD_GPIO::MUX_MODE.val(mode as u32)
418                        + SW_MUX_CTL_PAD_GPIO::SION.val(sion as u32),
419                );
420            }
421            PadId::SdB1 => {
422                self.registers.sw_mux_ctl_pad_gpio_sd_b1[pin].modify(
423                    SW_MUX_CTL_PAD_GPIO::MUX_MODE.val(mode as u32)
424                        + SW_MUX_CTL_PAD_GPIO::SION.val(sion as u32),
425                );
426            }
427        }
428    }
429
430    // Clear the functionality mode for a specific pad
431    pub fn disable_sw_mux_ctl_pad_gpio(&self, pad: PadId, pin: usize) {
432        match pad {
433            PadId::EMC => {
434                self.registers.sw_mux_ctl_pad_gpio_emc[pin].modify(
435                    SW_MUX_CTL_PAD_GPIO::MUX_MODE::CLEAR + SW_MUX_CTL_PAD_GPIO::SION::CLEAR,
436                );
437            }
438            PadId::AdB0 => {
439                self.registers.sw_mux_ctl_pad_gpio_ad_b0[pin].modify(
440                    SW_MUX_CTL_PAD_GPIO::MUX_MODE::CLEAR + SW_MUX_CTL_PAD_GPIO::SION::CLEAR,
441                );
442            }
443            PadId::AdB1 => {
444                self.registers.sw_mux_ctl_pad_gpio_ad_b1[pin].modify(
445                    SW_MUX_CTL_PAD_GPIO::MUX_MODE::CLEAR + SW_MUX_CTL_PAD_GPIO::SION::CLEAR,
446                );
447            }
448            PadId::B0 => {
449                self.registers.sw_mux_ctl_pad_gpio_b0[pin].modify(
450                    SW_MUX_CTL_PAD_GPIO::MUX_MODE::CLEAR + SW_MUX_CTL_PAD_GPIO::SION::CLEAR,
451                );
452            }
453            PadId::B1 => {
454                self.registers.sw_mux_ctl_pad_gpio_b1[pin].modify(
455                    SW_MUX_CTL_PAD_GPIO::MUX_MODE::CLEAR + SW_MUX_CTL_PAD_GPIO::SION::CLEAR,
456                );
457            }
458            PadId::SdB0 => {
459                self.registers.sw_mux_ctl_pad_gpio_sd_b0[pin].modify(
460                    SW_MUX_CTL_PAD_GPIO::MUX_MODE::CLEAR + SW_MUX_CTL_PAD_GPIO::SION::CLEAR,
461                );
462            }
463            PadId::SdB1 => {
464                self.registers.sw_mux_ctl_pad_gpio_sd_b1[pin].modify(
465                    SW_MUX_CTL_PAD_GPIO::MUX_MODE::CLEAR + SW_MUX_CTL_PAD_GPIO::SION::CLEAR,
466                );
467            }
468        }
469    }
470
471    // Configure electrical functionalities for a pad, such as pull up or pull down resistance,
472    // speed frequency, open drain, as explained above.
473    pub fn configure_sw_pad_ctl_pad_gpio(
474        &self,
475        pad: PadId,
476        pin: usize,
477        pus: PullUpDown,
478        pke: PullKeepEn,
479        ode: OpenDrainEn,
480        speed: Speed,
481        dse: DriveStrength,
482    ) {
483        match pad {
484            PadId::EMC => {
485                self.registers.sw_pad_ctl_pad_gpio_emc[pin].modify(
486                    SW_PAD_CTL_PAD_GPIO::PUS.val(pus as u32)
487                        + SW_PAD_CTL_PAD_GPIO::PKE.val(pke as u32)
488                        + SW_PAD_CTL_PAD_GPIO::ODE.val(ode as u32)
489                        + SW_PAD_CTL_PAD_GPIO::SPEED.val(speed as u32)
490                        + SW_PAD_CTL_PAD_GPIO::DSE.val(dse as u32),
491                );
492            }
493            PadId::AdB0 => {
494                self.registers.sw_pad_ctl_pad_gpio_ad_b0[pin].modify(
495                    SW_PAD_CTL_PAD_GPIO::PUS.val(pus as u32)
496                        + SW_PAD_CTL_PAD_GPIO::PKE.val(pke as u32)
497                        + SW_PAD_CTL_PAD_GPIO::ODE.val(ode as u32)
498                        + SW_PAD_CTL_PAD_GPIO::SPEED.val(speed as u32)
499                        + SW_PAD_CTL_PAD_GPIO::DSE.val(dse as u32),
500                );
501            }
502            PadId::AdB1 => {
503                self.registers.sw_pad_ctl_pad_gpio_ad_b1[pin].modify(
504                    SW_PAD_CTL_PAD_GPIO::PUS.val(pus as u32)
505                        + SW_PAD_CTL_PAD_GPIO::PKE.val(pke as u32)
506                        + SW_PAD_CTL_PAD_GPIO::ODE.val(ode as u32)
507                        + SW_PAD_CTL_PAD_GPIO::SPEED.val(speed as u32)
508                        + SW_PAD_CTL_PAD_GPIO::DSE.val(dse as u32),
509                );
510            }
511            PadId::B0 => {
512                self.registers.sw_pad_ctl_pad_gpio_b0[pin].modify(
513                    SW_PAD_CTL_PAD_GPIO::PUS.val(pus as u32)
514                        + SW_PAD_CTL_PAD_GPIO::PKE.val(pke as u32)
515                        + SW_PAD_CTL_PAD_GPIO::ODE.val(ode as u32)
516                        + SW_PAD_CTL_PAD_GPIO::SPEED.val(speed as u32)
517                        + SW_PAD_CTL_PAD_GPIO::DSE.val(dse as u32),
518                );
519            }
520            PadId::B1 => {
521                self.registers.sw_pad_ctl_pad_gpio_b1[pin].modify(
522                    SW_PAD_CTL_PAD_GPIO::PUS.val(pus as u32)
523                        + SW_PAD_CTL_PAD_GPIO::PKE.val(pke as u32)
524                        + SW_PAD_CTL_PAD_GPIO::ODE.val(ode as u32)
525                        + SW_PAD_CTL_PAD_GPIO::SPEED.val(speed as u32)
526                        + SW_PAD_CTL_PAD_GPIO::DSE.val(dse as u32),
527                );
528            }
529            PadId::SdB0 => {
530                self.registers.sw_pad_ctl_pad_gpio_sd_b0[pin].modify(
531                    SW_PAD_CTL_PAD_GPIO::PUS.val(pus as u32)
532                        + SW_PAD_CTL_PAD_GPIO::PKE.val(pke as u32)
533                        + SW_PAD_CTL_PAD_GPIO::ODE.val(ode as u32)
534                        + SW_PAD_CTL_PAD_GPIO::SPEED.val(speed as u32)
535                        + SW_PAD_CTL_PAD_GPIO::DSE.val(dse as u32),
536                );
537            }
538            PadId::SdB1 => {
539                self.registers.sw_pad_ctl_pad_gpio_sd_b1[pin].modify(
540                    SW_PAD_CTL_PAD_GPIO::PUS.val(pus as u32)
541                        + SW_PAD_CTL_PAD_GPIO::PKE.val(pke as u32)
542                        + SW_PAD_CTL_PAD_GPIO::ODE.val(ode as u32)
543                        + SW_PAD_CTL_PAD_GPIO::SPEED.val(speed as u32)
544                        + SW_PAD_CTL_PAD_GPIO::DSE.val(dse as u32),
545                );
546            }
547        }
548    }
549
550    // The following functions are used for altering the Daisy Chain which is used for
551    // multi pads driving same module input pin
552
553    // LPI2C1_SCL_SELECT_INPUT
554    pub fn is_enabled_lpi2c_scl_select_input(&self) -> bool {
555        self.registers
556            .lpi2c1_scl_select_input
557            .is_set(DAISY_SELECT_INPUT::DAISY)
558    }
559
560    pub fn enable_lpi2c_scl_select_input(&self) {
561        self.registers
562            .lpi2c1_scl_select_input
563            .modify(DAISY_SELECT_INPUT::DAISY::SET)
564    }
565
566    pub fn disable_lpi2c_scl_select_input(&self) {
567        self.registers
568            .lpi2c1_scl_select_input
569            .modify(DAISY_SELECT_INPUT::DAISY::CLEAR);
570    }
571
572    // LPI2C1_SDA_SELECT_INPUT
573    pub fn is_enabled_lpi2c_sda_select_input(&self) -> bool {
574        self.registers
575            .lpi2c1_sda_select_input
576            .is_set(DAISY_SELECT_INPUT::DAISY)
577    }
578
579    pub fn enable_lpi2c_sda_select_input(&self) {
580        self.registers
581            .lpi2c1_sda_select_input
582            .modify(DAISY_SELECT_INPUT::DAISY::SET)
583    }
584
585    pub fn disable_lpi2c_sda_select_input(&self) {
586        self.registers
587            .lpi2c1_sda_select_input
588            .modify(DAISY_SELECT_INPUT::DAISY::CLEAR);
589    }
590
591    // LPUART2_RX_SELECT_INPUT
592    pub fn is_enabled_lpuart2_rx_select_input(&self) -> bool {
593        self.registers
594            .lpuart2_rx_select_input
595            .is_set(DAISY_SELECT_INPUT::DAISY)
596    }
597    pub fn enable_lpuart2_rx_select_input(&self) {
598        self.registers
599            .lpuart2_rx_select_input
600            .modify(DAISY_SELECT_INPUT::DAISY::SET);
601    }
602
603    pub fn disable_lpuart2_rx_select_input(&self) {
604        self.registers
605            .lpuart2_rx_select_input
606            .modify(DAISY_SELECT_INPUT::DAISY::CLEAR);
607    }
608
609    // LPUART2_TX_SELECT_INPUT
610    pub fn is_enabled_lpuart2_tx_select_input(&self) -> bool {
611        self.registers
612            .lpuart2_tx_select_input
613            .is_set(DAISY_SELECT_INPUT::DAISY)
614    }
615    pub fn enable_lpuart2_tx_select_input(&self) {
616        self.registers
617            .lpuart2_tx_select_input
618            .modify(DAISY_SELECT_INPUT::DAISY::SET);
619    }
620
621    pub fn disable_lpuart2_tx_select_input(&self) {
622        self.registers
623            .lpuart2_tx_select_input
624            .modify(DAISY_SELECT_INPUT::DAISY::CLEAR);
625    }
626}
imxrt10xx/iomuxc.rs

imxrt10xx/
iomuxc.rs
