capsules_extra/cyw4343/bus/
mod.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright OxidOS Automotive 2025.
4
5//! Common interface for CYW4343x buses. The buses support 3 functions:
6//! F0: Standard bus function. These packets are used to write/read the chip's registers (e.g.
7//! disable overflow interrupts)
8//! F1: Backplane function. These packets are used to access the internal address space (e.g.
9//! writing the firmware)
10//! F2: WLAN function. These packets are used for WLAN data.
11//!
12//! F0 and F1 functions are used in the configuring/initialisation process of each bus
13//! implementation (setting up registers, loading binaries).
14//!
15//! F2 is used for reading/writing WLAN packets. The bus implementation should only handle
16//! sending data as F2 packets and it should expect that the SDPCM protocol headers have been added by
17//! the upper layer.
18//!
19//! The bus should be responsible for handling interrupts from the chip and notify the clients of
20//! incoming data with the `packet_available` method or with the `State::Available` state.
21
22use kernel::utilities::leasable_buffer::SubSliceMut;
23
24mod common;
25pub mod spi;
26
27/// Addresses (F0/F1/F2) are 32 bits
28pub type RegAddr = u32;
29
30/// Function of the incoming operation
31#[derive(Debug, Clone, Copy, PartialEq, Eq)]
32#[repr(u8)]
33pub enum Function {
34    /// Register access
35    Bus = 0b00,
36    /// Inner address space access
37    Backplane = 0b01,
38    /// WLAN packets
39    Wlan = 0b10,
40}
41
42/// Supported transfer types
43#[derive(Debug, Clone, Copy)]
44#[repr(u8)]
45pub enum Type {
46    Read = 0b0,
47    Write = 0b1,
48}
49
50/// Length of bytes to read/write in a register
51#[derive(Debug, Clone, Copy)]
52#[repr(u8)]
53pub enum RegLen {
54    Byte = 1,
55    HalfWord = 2,
56    Word = 4,
57}
58
59/// Current state of the bus
60#[derive(Clone, Copy, Debug)]
61pub enum State {
62    /// No incoming packet available
63    Idle,
64    /// CLient should wait for a `packet_available` call
65    Incoming,
66    /// A packet is now available to be read
67    Available(usize),
68}
69
70/// Trait for a bus that is used to communicate with CYW43xx device
71pub trait CYW4343xBus<'a> {
72    /// Set the client to be used for callbacks of the `Cyw43Bus` implementation
73    fn set_client(&self, client: &'a dyn CYW4343xBusClient);
74
75    /// Initialise the bus
76    fn init(&self) -> Result<(), kernel::ErrorCode>;
77
78    /// Write a WLAN (F2) packet
79    fn write_bytes(
80        &self,
81        buffer: SubSliceMut<'static, u8>,
82    ) -> Result<(), (kernel::ErrorCode, SubSliceMut<'static, u8>)>;
83
84    /// Read a WLAN (F2) packet if available.
85    fn read_bytes(
86        &self,
87        buffer: SubSliceMut<'static, u8>,
88        len: usize,
89    ) -> Result<(), (kernel::ErrorCode, SubSliceMut<'static, u8>)>;
90
91    /// Get current bus state
92    fn state(&self) -> Result<State, kernel::ErrorCode>;
93}
94
95/// Client trait for defining callbacks on initialisation, transfer
96/// and F2 packet interrupts.
97pub trait CYW4343xBusClient {
98    /// Initialisation process is done
99    fn init_done(&self, rval: Result<(), kernel::ErrorCode>);
100
101    /// WLAN write done
102    fn write_bytes_done(
103        &self,
104        buffer: SubSliceMut<'static, u8>,
105        rval: Result<(), kernel::ErrorCode>,
106    );
107
108    /// WLAN read done
109    fn read_bytes_done(
110        &self,
111        buffer: SubSliceMut<'static, u8>,
112        rval: Result<(), kernel::ErrorCode>,
113    );
114
115    /// An F2 (WLAN) packet is available
116    fn packet_available(&self, len: usize);
117}
capsules_extra/cyw4343/bus/mod.rs

capsules_extra/cyw4343/bus/
mod.rs
