apollo3/
pwrctrl.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Power Control driver.
6
7use kernel::utilities::registers::interfaces::{ReadWriteable, Readable};
8use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite};
9use kernel::utilities::StaticRef;
10
11const PWRCTRL_BASE: StaticRef<PwrCtrlRegisters> =
12    unsafe { StaticRef::new(0x4002_1000 as *const PwrCtrlRegisters) };
13
14register_structs! {
15    pub PwrCtrlRegisters {
16        (0x000 => supplysrc: ReadWrite<u32, SUPPLYSRC::Register>),
17        (0x004 => supplystatus: ReadWrite<u32, SUPPLYSTATUS::Register>),
18        (0x008 => devpwren: ReadWrite<u32, DEVPWREN::Register>),
19        (0x00c => mempwdinsleep: ReadWrite<u32>),
20        (0x010 => mempwren: ReadWrite<u32>),
21        (0x014 => mempwrstatus: ReadWrite<u32>),
22        (0x018 => devpwrstatus: ReadOnly<u32, DEVPWRSTATUS::Register>),
23        (0x01c => sramctrl: ReadWrite<u32>),
24        (0x020 => adcstatus: ReadWrite<u32>),
25        (0x024 => misc: ReadWrite<u32>),
26        (0x028 => devpwreventen: ReadWrite<u32>),
27        (0x02c => mempwreventen: ReadWrite<u32>),
28        (0x030 => @END),
29    }
30}
31
32register_bitfields![u32,
33    SUPPLYSRC [
34        BLEBUCKEN OFFSET(0) NUMBITS(8) []
35    ],
36    SUPPLYSTATUS [
37        SIMOBUCKON OFFSET(0) NUMBITS(1) [],
38        BLEBUCKON OFFSET(1) NUMBITS(1) []
39    ],
40    DEVPWREN [
41        PWRIOS OFFSET(0) NUMBITS(1) [],
42        PWRIOM0 OFFSET(1) NUMBITS(1) [],
43        PWRIOM1 OFFSET(2) NUMBITS(1) [],
44        PWRIOM2 OFFSET(3) NUMBITS(1) [],
45        PWRIOM3 OFFSET(4) NUMBITS(1) [],
46        PWRIOM4 OFFSET(5) NUMBITS(1) [],
47        PWRIOM5 OFFSET(6) NUMBITS(1) [],
48        PWRUART0 OFFSET(7) NUMBITS(1) [],
49        PWRUART1 OFFSET(8) NUMBITS(1) [],
50        PWRADC OFFSET(9) NUMBITS(1) [],
51        PWRSCARD OFFSET(10) NUMBITS(1) [],
52        PWRMSPI OFFSET(11) NUMBITS(1) [],
53        PWRPDM OFFSET(12) NUMBITS(1) [],
54        PWRBLEL OFFSET(13) NUMBITS(1) []
55    ],
56    DEVPWRSTATUS [
57        MCUL OFFSET(0) NUMBITS(1) [],
58        MCUH OFFSET(1) NUMBITS(1) [],
59        HCPA OFFSET(2) NUMBITS(1) [],
60        HCPB OFFSET(3) NUMBITS(1) [],
61        HCPC OFFSET(4) NUMBITS(1) [],
62        PWRADC OFFSET(5) NUMBITS(1) [],
63        PWRMSPI OFFSET(6) NUMBITS(1) [],
64        PWRPDM OFFSET(7) NUMBITS(1) [],
65        BLEL OFFSET(8) NUMBITS(1) [],
66        BLEH OFFSET(9) NUMBITS(1) [],
67        CORESLEEP OFFSET(29) NUMBITS(1) [],
68        COREDEEPSLEEP OFFSET(30) NUMBITS(1) [],
69        SYSDEEPSLEEP OFFSET(31) NUMBITS(1) []
70    ]
71];
72
73pub struct PwrCtrl {
74    registers: StaticRef<PwrCtrlRegisters>,
75}
76
77impl PwrCtrl {
78    pub const fn new() -> PwrCtrl {
79        PwrCtrl {
80            registers: PWRCTRL_BASE,
81        }
82    }
83
84    pub fn enable_uart0(&self) {
85        let regs = self.registers;
86
87        regs.devpwren.modify(DEVPWREN::PWRUART0::SET);
88    }
89
90    pub fn enable_ios(&self) {
91        let regs = self.registers;
92
93        regs.devpwren.modify(DEVPWREN::PWRIOS::SET);
94    }
95
96    pub fn enable_iom0(&self) {
97        let regs = self.registers;
98
99        regs.devpwren.modify(DEVPWREN::PWRIOM0::SET);
100    }
101
102    pub fn enable_iom1(&self) {
103        let regs = self.registers;
104
105        regs.devpwren.modify(DEVPWREN::PWRIOM1::SET);
106    }
107
108    pub fn enable_iom2(&self) {
109        let regs = self.registers;
110
111        regs.devpwren.modify(DEVPWREN::PWRIOM2::SET);
112    }
113
114    pub fn enable_iom3(&self) {
115        let regs = self.registers;
116
117        regs.devpwren.modify(DEVPWREN::PWRIOM3::SET);
118    }
119
120    pub fn enable_iom4(&self) {
121        let regs = self.registers;
122
123        regs.devpwren.modify(DEVPWREN::PWRIOM4::SET);
124    }
125
126    pub fn enable_ble(&self) {
127        let regs = self.registers;
128
129        regs.devpwren.modify(DEVPWREN::PWRBLEL::SET);
130
131        while !regs.devpwrstatus.is_set(DEVPWRSTATUS::BLEL) {}
132    }
133}
apollo3/pwrctrl.rs

apollo3/
pwrctrl.rs
