apollo3/
cachectrl.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Cache Control driver.
6
7use kernel::utilities::registers::interfaces::Writeable;
8use kernel::utilities::registers::{register_bitfields, register_structs, ReadWrite};
9use kernel::utilities::StaticRef;
10
11const CACHECTRL_BASE: StaticRef<CacheCtrlRegisters> =
12    unsafe { StaticRef::new(0x4001_8000 as *const CacheCtrlRegisters) };
13
14register_structs! {
15    pub CacheCtrlRegisters {
16        (0x00 => cachecfg: ReadWrite<u32, CACHECFG::Register>),
17        (0x04 => flashcfg: ReadWrite<u32>),
18        (0x08 => ctrl: ReadWrite<u32>),
19        (0x0C => _reserved0),
20        (0x10 => ncr0start: ReadWrite<u32>),
21        (0x14 => ncr0end: ReadWrite<u32>),
22        (0x18 => ncr1start: ReadWrite<u32>),
23        (0x1C => ncr1end: ReadWrite<u32>),
24        (0x20 => _reserved1),
25        (0x40 => dmon0: ReadWrite<u32>),
26        (0x44 => dmon1: ReadWrite<u32>),
27        (0x48 => dmon2: ReadWrite<u32>),
28        (0x4C => dmon3: ReadWrite<u32>),
29        (0x50 => imon0: ReadWrite<u32>),
30        (0x54 => imon1: ReadWrite<u32>),
31        (0x58 => imon2: ReadWrite<u32>),
32        (0x5C => imon3: ReadWrite<u32>),
33        (0x60 => @END),
34    }
35}
36
37register_bitfields![u32,
38    CACHECFG [
39        ENABLE OFFSET(0) NUMBITS(1) [],
40        LRU OFFSET(1) NUMBITS(1) [],
41        ENABLE_NC0 OFFSET(2) NUMBITS(1) [],
42        ENABLE_NC1 OFFSET(3) NUMBITS(1) [],
43        CONFIG OFFSET(4) NUMBITS(4) [],
44        ICACHE_ENABLE OFFSET(8) NUMBITS(1) [],
45        DCACHE_ENABLE OFFSET(9) NUMBITS(1) [],
46        CACHE_CLKGATE OFFSET(10) NUMBITS(1) [],
47        CACHE_LS OFFSET(11) NUMBITS(1) [],
48        DATA_CLK_GATE OFFSET(20) NUMBITS(1) [],
49        ENABLE_MONITOR OFFSET(24) NUMBITS(1) []
50    ]
51];
52
53pub struct CacheCtrl {
54    registers: StaticRef<CacheCtrlRegisters>,
55}
56
57impl CacheCtrl {
58    pub const fn new() -> CacheCtrl {
59        CacheCtrl {
60            registers: CACHECTRL_BASE,
61        }
62    }
63
64    pub fn enable_cache(&self) {
65        self.registers.cachecfg.write(
66            CACHECFG::ENABLE::SET
67                + CACHECFG::CACHE_CLKGATE::SET
68                + CACHECFG::DATA_CLK_GATE::SET
69                + CACHECFG::ICACHE_ENABLE::SET
70                + CACHECFG::DCACHE_ENABLE::SET,
71        );
72    }
73}
apollo3/cachectrl.rs

apollo3/
cachectrl.rs
